2 a84cbb2a 2004-04-19 devnull * 386 definition
4 a84cbb2a 2004-04-19 devnull #include <u.h>
5 a84cbb2a 2004-04-19 devnull #include <libc.h>
6 a84cbb2a 2004-04-19 devnull #include <bio.h>
7 a84cbb2a 2004-04-19 devnull #include <mach.h>
8 a84cbb2a 2004-04-19 devnull #include "ureg386.h"
10 a84cbb2a 2004-04-19 devnull #define REGOFF(x) (ulong)(&((struct Ureg *) 0)->x)
12 a84cbb2a 2004-04-19 devnull #define REGSIZE sizeof(struct Ureg)
13 a84cbb2a 2004-04-19 devnull #define FP_CTL(x) (REGSIZE+4*(x))
14 a84cbb2a 2004-04-19 devnull #define FP_REG(x) (FP_CTL(7)+10*(x))
15 a84cbb2a 2004-04-19 devnull #define FPREGSIZE (6*4+8*10)
18 a84cbb2a 2004-04-19 devnull * i386-specific debugger interface
21 443d6288 2012-02-19 rsc char *i386excep(Map*, Regs*);
24 a84cbb2a 2004-04-19 devnull static int i386trace(Map*, ulong, ulong, ulong, Tracer);
25 a84cbb2a 2004-04-19 devnull static ulong i386frame(Map*, ulong, ulong, ulong, ulong);
27 443d6288 2012-02-19 rsc int i386foll(Map*, Regs*, u64int, u64int*);
28 443d6288 2012-02-19 rsc int i386hexinst(Map*, u64int, char*, int);
29 443d6288 2012-02-19 rsc int i386das(Map*, u64int, char, char*, int);
30 443d6288 2012-02-19 rsc int i386instlen(Map*, u64int);
31 443d6288 2012-02-19 rsc int i386unwind(Map*, Regs*, u64int*, Symbol*);
33 cbeb0b26 2006-04-01 devnull static char *i386windregs[] = {
46 a84cbb2a 2004-04-19 devnull static Regdesc i386reglist[] = {
47 a84cbb2a 2004-04-19 devnull {"DI", REGOFF(di), RINT, 'X'},
48 a84cbb2a 2004-04-19 devnull {"SI", REGOFF(si), RINT, 'X'},
49 a84cbb2a 2004-04-19 devnull {"BP", REGOFF(bp), RINT, 'X'},
50 a84cbb2a 2004-04-19 devnull {"BX", REGOFF(bx), RINT, 'X'},
51 a84cbb2a 2004-04-19 devnull {"DX", REGOFF(dx), RINT, 'X'},
52 a84cbb2a 2004-04-19 devnull {"CX", REGOFF(cx), RINT, 'X'},
53 a84cbb2a 2004-04-19 devnull {"AX", REGOFF(ax), RINT, 'X'},
54 a84cbb2a 2004-04-19 devnull {"GS", REGOFF(gs), RINT, 'X'},
55 a84cbb2a 2004-04-19 devnull {"FS", REGOFF(fs), RINT, 'X'},
56 a84cbb2a 2004-04-19 devnull {"ES", REGOFF(es), RINT, 'X'},
57 a84cbb2a 2004-04-19 devnull {"DS", REGOFF(ds), RINT, 'X'},
58 a84cbb2a 2004-04-19 devnull {"TRAP", REGOFF(trap), RINT, 'X'},
59 a84cbb2a 2004-04-19 devnull {"ECODE", REGOFF(ecode), RINT, 'X'},
60 a84cbb2a 2004-04-19 devnull {"PC", REGOFF(pc), RINT, 'X'},
61 a84cbb2a 2004-04-19 devnull {"CS", REGOFF(cs), RINT, 'X'},
62 a84cbb2a 2004-04-19 devnull {"EFLAGS", REGOFF(flags), RINT, 'X'},
63 a84cbb2a 2004-04-19 devnull {"SP", REGOFF(sp), RINT, 'X'},
64 a84cbb2a 2004-04-19 devnull {"SS", REGOFF(ss), RINT, 'X'},
66 a84cbb2a 2004-04-19 devnull {"E0", FP_CTL(0), RFLT, 'X'},
67 a84cbb2a 2004-04-19 devnull {"E1", FP_CTL(1), RFLT, 'X'},
68 a84cbb2a 2004-04-19 devnull {"E2", FP_CTL(2), RFLT, 'X'},
69 a84cbb2a 2004-04-19 devnull {"E3", FP_CTL(3), RFLT, 'X'},
70 a84cbb2a 2004-04-19 devnull {"E4", FP_CTL(4), RFLT, 'X'},
71 a84cbb2a 2004-04-19 devnull {"E5", FP_CTL(5), RFLT, 'X'},
72 a84cbb2a 2004-04-19 devnull {"E6", FP_CTL(6), RFLT, 'X'},
73 a84cbb2a 2004-04-19 devnull {"F0", FP_REG(7), RFLT, '3'},
74 a84cbb2a 2004-04-19 devnull {"F1", FP_REG(6), RFLT, '3'},
75 a84cbb2a 2004-04-19 devnull {"F2", FP_REG(5), RFLT, '3'},
76 a84cbb2a 2004-04-19 devnull {"F3", FP_REG(4), RFLT, '3'},
77 a84cbb2a 2004-04-19 devnull {"F4", FP_REG(3), RFLT, '3'},
78 a84cbb2a 2004-04-19 devnull {"F5", FP_REG(2), RFLT, '3'},
79 a84cbb2a 2004-04-19 devnull {"F6", FP_REG(1), RFLT, '3'},
80 a84cbb2a 2004-04-19 devnull {"F7", FP_REG(0), RFLT, '3'},
84 a84cbb2a 2004-04-19 devnull Mach mach386 =
87 a84cbb2a 2004-04-19 devnull M386, /* machine type */
88 a84cbb2a 2004-04-19 devnull i386reglist, /* register list */
89 a84cbb2a 2004-04-19 devnull REGSIZE, /* size of registers in bytes */
90 a84cbb2a 2004-04-19 devnull FPREGSIZE, /* size of fp registers in bytes */
91 a84cbb2a 2004-04-19 devnull "PC", /* name of PC */
92 a84cbb2a 2004-04-19 devnull "SP", /* name of SP */
93 a84cbb2a 2004-04-19 devnull "BP", /* name of FP */
94 a84cbb2a 2004-04-19 devnull 0, /* link register */
95 a84cbb2a 2004-04-19 devnull "setSB", /* static base register name (bogus anyways) */
96 a84cbb2a 2004-04-19 devnull 0, /* static base register value */
97 a84cbb2a 2004-04-19 devnull 0x1000, /* page size */
98 a84cbb2a 2004-04-19 devnull 0x80100000, /* kernel base */
99 a84cbb2a 2004-04-19 devnull 0, /* kernel text mask */
100 a84cbb2a 2004-04-19 devnull 1, /* quantization of pc */
101 a84cbb2a 2004-04-19 devnull 4, /* szaddr */
102 a84cbb2a 2004-04-19 devnull 4, /* szreg */
103 a84cbb2a 2004-04-19 devnull 4, /* szfloat */
104 a84cbb2a 2004-04-19 devnull 8, /* szdouble */
106 a84cbb2a 2004-04-19 devnull i386windregs, /* locations unwound in stack trace */
109 a84cbb2a 2004-04-19 devnull {0xCC, 0, 0, 0}, /* break point: INT 3 */
110 a84cbb2a 2004-04-19 devnull 1, /* break point size */
112 a84cbb2a 2004-04-19 devnull i386foll, /* following addresses */
113 a84cbb2a 2004-04-19 devnull i386excep, /* print exception */
114 a84cbb2a 2004-04-19 devnull i386unwind, /* stack unwind */
116 a84cbb2a 2004-04-19 devnull leswap2, /* convert short to local byte order */
117 a84cbb2a 2004-04-19 devnull leswap4, /* convert long to local byte order */
118 a84cbb2a 2004-04-19 devnull leswap8, /* convert vlong to local byte order */
119 a84cbb2a 2004-04-19 devnull leieeeftoa32, /* single precision float pointer */
120 a84cbb2a 2004-04-19 devnull leieeeftoa64, /* double precision float pointer */
121 a84cbb2a 2004-04-19 devnull leieeeftoa80, /* long double precision floating point */
123 a84cbb2a 2004-04-19 devnull i386das, /* dissembler */
124 a84cbb2a 2004-04-19 devnull i386das, /* plan9-format disassembler */
125 a84cbb2a 2004-04-19 devnull 0, /* commercial disassembler */
126 a84cbb2a 2004-04-19 devnull i386hexinst, /* print instruction */
127 a84cbb2a 2004-04-19 devnull i386instlen, /* instruction size calculation */
131 fa325e9b 2020-01-10 cross * The wrapper code around Linux system calls
132 1cc215aa 2004-12-25 devnull * saves AX on the stack before calling some calls
133 fa325e9b 2020-01-10 cross * (at least, __libc_nanosleep), when running in
134 fa325e9b 2020-01-10 cross * threaded programs.
136 1cc215aa 2004-12-25 devnull static void
137 1cc215aa 2004-12-25 devnull syscallhack(Map *map, Regs *regs, int *spoff)
140 1cc215aa 2004-12-25 devnull char buf[60];
142 1cc215aa 2004-12-25 devnull rget(regs, "PC", &pc);
143 1cc215aa 2004-12-25 devnull if(i386das(map, pc-2, 0, buf, sizeof buf) != 2 || strncmp(buf, "INTB\t$", 6) != 0)
145 1cc215aa 2004-12-25 devnull if(i386das(map, pc, 0, buf, sizeof buf) != 2 || strcmp(buf, "MOVL\tDX,BX") != 0)
147 1cc215aa 2004-12-25 devnull if(i386das(map, pc+2, 0, buf, sizeof buf) != 3 || strcmp(buf, "XCHGL\tAX,0(SP)") != 0)
149 fa325e9b 2020-01-10 cross *spoff += 4;
153 443d6288 2012-02-19 rsc i386unwind(Map *map, Regs *regs, u64int *next, Symbol *sym)
155 1cc215aa 2004-12-25 devnull int i, isp, ipc, ibp, havebp, n, spoff, off[9];
156 1cc215aa 2004-12-25 devnull ulong pc;
157 a84cbb2a 2004-04-19 devnull u32int v;
158 1cc215aa 2004-12-25 devnull char buf[60], *p;
160 cbeb0b26 2006-04-01 devnull /*print("i386unwind %s\n", sym ? sym->name : nil); */
161 a84cbb2a 2004-04-19 devnull isp = windindex("SP");
162 a84cbb2a 2004-04-19 devnull ipc = windindex("PC");
163 a84cbb2a 2004-04-19 devnull ibp = windindex("BP");
164 a84cbb2a 2004-04-19 devnull if(isp < 0 || ipc < 0 || ibp < 0){
165 a84cbb2a 2004-04-19 devnull werrstr("i386unwind: cannot happen");
166 a84cbb2a 2004-04-19 devnull return -1;
170 1cc215aa 2004-12-25 devnull * Disassemble entry to figure out
171 1cc215aa 2004-12-25 devnull * where values have been saved.
172 1cc215aa 2004-12-25 devnull * Perhaps should disassemble exit path
173 1cc215aa 2004-12-25 devnull * instead -- a random walk on the code
174 1cc215aa 2004-12-25 devnull * should suffice to get us to a RET.
176 1cc215aa 2004-12-25 devnull if(sym){
177 1cc215aa 2004-12-25 devnull pc = sym->loc.addr;
178 cbeb0b26 2006-04-01 devnull /*print("startpc %lux\n", pc); */
179 1cc215aa 2004-12-25 devnull memset(off, 0xff, sizeof off);
180 1cc215aa 2004-12-25 devnull spoff = 0;
181 1cc215aa 2004-12-25 devnull havebp = 0;
182 1cc215aa 2004-12-25 devnull for(;;){
183 1cc215aa 2004-12-25 devnull if((n = i386das(map, pc, 0, buf, sizeof buf)) < 0)
185 cbeb0b26 2006-04-01 devnull /*print("%s\n", buf); */
186 1cc215aa 2004-12-25 devnull pc += n;
187 1cc215aa 2004-12-25 devnull if(strncmp(buf, "PUSHL\t", 6) == 0){
188 1cc215aa 2004-12-25 devnull spoff += 4;
189 1cc215aa 2004-12-25 devnull if((i = windindex(buf+6)) >= 0)
190 1cc215aa 2004-12-25 devnull off[i] = spoff;
191 1cc215aa 2004-12-25 devnull }else if(strcmp(buf, "MOVL\tSP,BP") == 0 && spoff == 4 && off[ibp] == 4){
192 1cc215aa 2004-12-25 devnull havebp = 1;
193 1cc215aa 2004-12-25 devnull }else if(strncmp(buf, "SUBL\t$", 6) == 0){
194 1cc215aa 2004-12-25 devnull if((p = strrchr(buf, ',')) && strcmp(p, ",SP") == 0){
195 cbeb0b26 2006-04-01 devnull /*print("spoff %s\n", buf+6); */
196 1cc215aa 2004-12-25 devnull spoff += strtol(buf+6, 0, 16);
199 1cc215aa 2004-12-25 devnull }else if(strncmp(buf, "XORL\t", 5) == 0 || strncmp(buf, "MOVL\t", 5) == 0){
201 1cc215aa 2004-12-25 devnull * Hope these are rescheduled non-prologue instructions
202 1cc215aa 2004-12-25 devnull * like XORL AX, AX or MOVL $0x3, AX and thus ignorable.
208 1cc215aa 2004-12-25 devnull syscallhack(map, regs, &spoff);
210 1cc215aa 2004-12-25 devnull if(havebp){
211 cbeb0b26 2006-04-01 devnull /*print("havebp\n"); */
212 1cc215aa 2004-12-25 devnull rget(regs, "BP", &next[isp]);
213 1cc215aa 2004-12-25 devnull get4(map, next[isp], &v);
214 1cc215aa 2004-12-25 devnull next[ibp] = v;
215 1cc215aa 2004-12-25 devnull next[isp] += 4;
217 1cc215aa 2004-12-25 devnull rget(regs, "SP", &next[isp]);
218 cbeb0b26 2006-04-01 devnull /*print("old sp %lux + %d\n", next[isp], spoff); */
219 1cc215aa 2004-12-25 devnull next[isp] += spoff;
221 1cc215aa 2004-12-25 devnull for(i=0; i<nelem(off); i++)
222 1cc215aa 2004-12-25 devnull if(off[i] != -1){
223 1cc215aa 2004-12-25 devnull get4(map, next[isp]-off[i], &v);
224 1cc215aa 2004-12-25 devnull next[i] = v;
227 1cc215aa 2004-12-25 devnull if(get4(map, next[isp], &v) < 0)
228 1cc215aa 2004-12-25 devnull return -1;
229 cbeb0b26 2006-04-01 devnull /*print("new pc %lux => %lux\n", next[isp], v); */
230 1cc215aa 2004-12-25 devnull next[ipc] = v;
231 1cc215aa 2004-12-25 devnull next[isp] += 4;
232 1cc215aa 2004-12-25 devnull return 0;
236 1cc215aa 2004-12-25 devnull * Rely on bp chaining
238 1cc215aa 2004-12-25 devnull if(rget(regs, "BP", &next[isp]) < 0
239 1cc215aa 2004-12-25 devnull || get4(map, next[isp], &v) < 0)
240 a84cbb2a 2004-04-19 devnull return -1;
241 1cc215aa 2004-12-25 devnull next[ibp] = v;
242 1cc215aa 2004-12-25 devnull next[isp] += 4;
243 1cc215aa 2004-12-25 devnull if(get4(map, next[isp], &v) < 0)
244 1cc215aa 2004-12-25 devnull return -1;
245 a84cbb2a 2004-04-19 devnull next[ipc] = v;
246 1cc215aa 2004-12-25 devnull next[isp] += 4;
247 1cc215aa 2004-12-25 devnull return 0;
250 cbeb0b26 2006-04-01 devnull /*static char STARTSYM[] = "_main"; */
251 cbeb0b26 2006-04-01 devnull /*static char PROFSYM[] = "_mainp"; */
252 a84cbb2a 2004-04-19 devnull static char FRAMENAME[] = ".frame";
253 a84cbb2a 2004-04-19 devnull static char *excname[] =
255 20b33daf 2004-04-20 devnull "divide error", /* 0 */
256 20b33daf 2004-04-20 devnull "debug exception", /* 1 */
257 20b33daf 2004-04-20 devnull 0,0, /* 2, 3 */
258 20b33daf 2004-04-20 devnull "overflow", /* 4 */
259 20b33daf 2004-04-20 devnull "bounds check", /* 5 */
260 20b33daf 2004-04-20 devnull "invalid opcode", /* 6 */
261 20b33daf 2004-04-20 devnull "math coprocessor emulation", /* 7 */
262 20b33daf 2004-04-20 devnull "double fault", /* 8 */
263 20b33daf 2004-04-20 devnull "math coprocessor overrun", /* 9 */
264 20b33daf 2004-04-20 devnull "invalid TSS", /* 10 */
265 20b33daf 2004-04-20 devnull "segment not present", /* 11 */
266 20b33daf 2004-04-20 devnull "stack exception", /* 12 */
267 20b33daf 2004-04-20 devnull "general protection violation", /* 13 */
268 20b33daf 2004-04-20 devnull "page fault", /* 14 */
269 20b33daf 2004-04-20 devnull 0, /* 15 */
270 20b33daf 2004-04-20 devnull "math coprocessor error", /* 16 */
271 20b33daf 2004-04-20 devnull 0,0,0,0,0,0,0, /* 17-23 */
272 20b33daf 2004-04-20 devnull "clock", /* 24 */
273 20b33daf 2004-04-20 devnull "keyboard", /* 25 */
274 20b33daf 2004-04-20 devnull 0, /* 26 */
275 20b33daf 2004-04-20 devnull "modem status", /* 27 */
276 20b33daf 2004-04-20 devnull "serial line status", /* 28 */
277 20b33daf 2004-04-20 devnull 0, /* 29 */
278 20b33daf 2004-04-20 devnull "floppy disk", /* 30 */
279 20b33daf 2004-04-20 devnull 0,0,0,0,0, /* 31-35 */
280 20b33daf 2004-04-20 devnull "mouse", /* 36 */
281 20b33daf 2004-04-20 devnull "math coprocessor", /* 37 */
282 20b33daf 2004-04-20 devnull "hard disk", /* 38 */
283 20b33daf 2004-04-20 devnull 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,/* 39-54 */
284 20b33daf 2004-04-20 devnull 0,0,0,0,0,0,0,0,0, /* 55-63 */
285 20b33daf 2004-04-20 devnull "system call", /* 64 */
289 a84cbb2a 2004-04-19 devnull i386excep(Map *map, Regs *regs)
293 a84cbb2a 2004-04-19 devnull static char buf[16];
295 a84cbb2a 2004-04-19 devnull if(rget(regs, "TRAP", &c) < 0)
296 a84cbb2a 2004-04-19 devnull return "no trap register";
298 a84cbb2a 2004-04-19 devnull if(c > 64 || excname[c] == 0) {
299 a84cbb2a 2004-04-19 devnull if (c == 3) {
300 a84cbb2a 2004-04-19 devnull if (rget(regs, "PC", &pc) >= 0)
301 a84cbb2a 2004-04-19 devnull if (get1(map, pc, (uchar*)buf, mach->bpsize) > 0)
302 a84cbb2a 2004-04-19 devnull if (memcmp(buf, mach->bpinst, mach->bpsize) == 0)
303 a84cbb2a 2004-04-19 devnull return "breakpoint";
305 a84cbb2a 2004-04-19 devnull sprint(buf, "exception %ld", c);
306 a84cbb2a 2004-04-19 devnull return buf;
308 a84cbb2a 2004-04-19 devnull return excname[c];
311 a84cbb2a 2004-04-19 devnull /* I386/486 - Disassembler and related functions */
314 a84cbb2a 2004-04-19 devnull * an instruction
316 a84cbb2a 2004-04-19 devnull typedef struct Instr Instr;
317 a84cbb2a 2004-04-19 devnull struct Instr
319 a84cbb2a 2004-04-19 devnull uchar mem[1+1+1+1+2+1+1+4+4]; /* raw instruction */
320 443d6288 2012-02-19 rsc uvlong addr; /* address of start of instruction */
321 a84cbb2a 2004-04-19 devnull int n; /* number of bytes in instruction */
322 a84cbb2a 2004-04-19 devnull char *prefix; /* instr prefix */
323 a84cbb2a 2004-04-19 devnull char *segment; /* segment override */
324 a84cbb2a 2004-04-19 devnull uchar jumptype; /* set to the operand type for jump/ret/call */
325 443d6288 2012-02-19 rsc uchar amd64;
326 443d6288 2012-02-19 rsc uchar rex; /* REX prefix (or zero) */
327 443d6288 2012-02-19 rsc char osize; /* 'W' or 'L' (or 'Q' on amd64) */
328 443d6288 2012-02-19 rsc char asize; /* address size 'W' or 'L' (or 'Q' or amd64) */
329 a84cbb2a 2004-04-19 devnull uchar mod; /* bits 6-7 of mod r/m field */
330 a84cbb2a 2004-04-19 devnull uchar reg; /* bits 3-5 of mod r/m field */
331 443d6288 2012-02-19 rsc char ss; /* bits 6-7 of SIB */
332 1c171e3a 2005-07-19 devnull schar index; /* bits 3-5 of SIB */
333 1c171e3a 2005-07-19 devnull schar base; /* bits 0-2 of SIB */
334 443d6288 2012-02-19 rsc char rip; /* RIP-relative in amd64 mode */
335 443d6288 2012-02-19 rsc uchar opre; /* f2/f3 could introduce media */
336 a84cbb2a 2004-04-19 devnull short seg; /* segment of far address */
337 443d6288 2012-02-19 rsc uint32 disp; /* displacement */
338 443d6288 2012-02-19 rsc uint32 imm; /* immediate */
339 443d6288 2012-02-19 rsc uint32 imm2; /* second immediate operand */
340 443d6288 2012-02-19 rsc uvlong imm64; /* big immediate */
341 a84cbb2a 2004-04-19 devnull char *curr; /* fill level in output buffer */
342 a84cbb2a 2004-04-19 devnull char *end; /* end of output buffer */
343 a84cbb2a 2004-04-19 devnull char *err; /* error message */
346 a84cbb2a 2004-04-19 devnull /* 386 register (ha!) set */
358 443d6288 2012-02-19 rsc /* be careful: some unix system headers #define R8, R9, etc */
369 443d6288 2012-02-19 rsc /* amd64 rex extension byte */
371 443d6288 2012-02-19 rsc REXW = 1<<3, /* =1, 64-bit operand size */
372 443d6288 2012-02-19 rsc REXR = 1<<2, /* extend modrm reg */
373 443d6288 2012-02-19 rsc REXX = 1<<1, /* extend sib index */
374 443d6288 2012-02-19 rsc REXB = 1<<0 /* extend modrm r/m, sib base, or opcode reg */
377 a84cbb2a 2004-04-19 devnull /* Operand Format codes */
379 a84cbb2a 2004-04-19 devnull %A - address size register modifier (!asize -> 'E')
380 a84cbb2a 2004-04-19 devnull %C - Control register CR0/CR1/CR2
381 a84cbb2a 2004-04-19 devnull %D - Debug register DR0/DR1/DR2/DR3/DR6/DR7
382 a84cbb2a 2004-04-19 devnull %I - second immediate operand
383 a84cbb2a 2004-04-19 devnull %O - Operand size register modifier (!osize -> 'E')
384 a84cbb2a 2004-04-19 devnull %T - Test register TR6/TR7
385 a84cbb2a 2004-04-19 devnull %S - size code ('W' or 'L')
386 443d6288 2012-02-19 rsc %W - Weird opcode: OSIZE == 'W' => "CBW"; else => "CWDE"
387 a84cbb2a 2004-04-19 devnull %d - displacement 16-32 bits
388 a84cbb2a 2004-04-19 devnull %e - effective address - Mod R/M value
389 a84cbb2a 2004-04-19 devnull %f - floating point register F0-F7 - from Mod R/M register
390 a84cbb2a 2004-04-19 devnull %g - segment register
391 a84cbb2a 2004-04-19 devnull %i - immediate operand 8-32 bits
392 a84cbb2a 2004-04-19 devnull %p - PC-relative - signed displacement in immediate field
393 a84cbb2a 2004-04-19 devnull %r - Reg from Mod R/M
394 443d6288 2012-02-19 rsc %w - Weird opcode: OSIZE == 'W' => "CWD"; else => "CDQ"
397 a84cbb2a 2004-04-19 devnull typedef struct Optable Optable;
398 a84cbb2a 2004-04-19 devnull struct Optable
400 a84cbb2a 2004-04-19 devnull char operand[2];
401 a84cbb2a 2004-04-19 devnull void *proto; /* actually either (char*) or (Optable*) */
403 a84cbb2a 2004-04-19 devnull /* Operand decoding codes */
405 a84cbb2a 2004-04-19 devnull Ib = 1, /* 8-bit immediate - (no sign extension)*/
406 a84cbb2a 2004-04-19 devnull Ibs, /* 8-bit immediate (sign extended) */
407 a84cbb2a 2004-04-19 devnull Jbs, /* 8-bit sign-extended immediate in jump or call */
408 a84cbb2a 2004-04-19 devnull Iw, /* 16-bit immediate -> imm */
409 a84cbb2a 2004-04-19 devnull Iw2, /* 16-bit immediate -> imm2 */
410 a84cbb2a 2004-04-19 devnull Iwd, /* Operand-sized immediate (no sign extension)*/
411 443d6288 2012-02-19 rsc Iwdq, /* Operand-sized immediate, possibly 64 bits */
412 a84cbb2a 2004-04-19 devnull Awd, /* Address offset */
413 a84cbb2a 2004-04-19 devnull Iwds, /* Operand-sized immediate (sign extended) */
414 443d6288 2012-02-19 rsc RM, /* Word or int32 R/M field with register (/r) */
415 a84cbb2a 2004-04-19 devnull RMB, /* Byte R/M field with register (/r) */
416 443d6288 2012-02-19 rsc RMOP, /* Word or int32 R/M field with op code (/digit) */
417 a84cbb2a 2004-04-19 devnull RMOPB, /* Byte R/M field with op code (/digit) */
418 a84cbb2a 2004-04-19 devnull RMR, /* R/M register only (mod = 11) */
419 a84cbb2a 2004-04-19 devnull RMM, /* R/M memory only (mod = 0/1/2) */
420 443d6288 2012-02-19 rsc Op_R0, /* Base reg of Mod R/M is literal 0x00 */
421 443d6288 2012-02-19 rsc Op_R1, /* Base reg of Mod R/M is literal 0x01 */
422 a84cbb2a 2004-04-19 devnull FRMOP, /* Floating point R/M field with opcode */
423 a84cbb2a 2004-04-19 devnull FRMEX, /* Extended floating point R/M field with opcode */
424 a84cbb2a 2004-04-19 devnull JUMP, /* Jump or Call flag - no operand */
425 a84cbb2a 2004-04-19 devnull RET, /* Return flag - no operand */
426 a84cbb2a 2004-04-19 devnull OA, /* literal 0x0a byte */
427 a84cbb2a 2004-04-19 devnull PTR, /* Seg:Displacement addr (ptr16:16 or ptr16:32) */
428 a84cbb2a 2004-04-19 devnull AUX, /* Multi-byte op code - Auxiliary table */
429 443d6288 2012-02-19 rsc AUXMM, /* multi-byte op code - auxiliary table chosen by prefix */
430 a84cbb2a 2004-04-19 devnull PRE, /* Instr Prefix */
431 443d6288 2012-02-19 rsc OPRE, /* Instr Prefix or media op extension */
432 a84cbb2a 2004-04-19 devnull SEG, /* Segment Prefix */
433 a84cbb2a 2004-04-19 devnull OPOVER, /* Operand size override */
434 443d6288 2012-02-19 rsc ADDOVER, /* Address size override */
437 a84cbb2a 2004-04-19 devnull static Optable optab0F00[8]=
439 443d6288 2012-02-19 rsc [0x00] = { 0,0, "MOVW LDT,%e" },
440 443d6288 2012-02-19 rsc [0x01] = { 0,0, "MOVW TR,%e" },
441 443d6288 2012-02-19 rsc [0x02] = { 0,0, "MOVW %e,LDT" },
442 443d6288 2012-02-19 rsc [0x03] = { 0,0, "MOVW %e,TR" },
443 443d6288 2012-02-19 rsc [0x04] = { 0,0, "VERR %e" },
444 443d6288 2012-02-19 rsc [0x05] = { 0,0, "VERW %e" },
447 a84cbb2a 2004-04-19 devnull static Optable optab0F01[8]=
449 443d6288 2012-02-19 rsc [0x00] = { 0,0, "MOVL GDTR,%e" },
450 443d6288 2012-02-19 rsc [0x01] = { 0,0, "MOVL IDTR,%e" },
451 443d6288 2012-02-19 rsc [0x02] = { 0,0, "MOVL %e,GDTR" },
452 443d6288 2012-02-19 rsc [0x03] = { 0,0, "MOVL %e,IDTR" },
453 443d6288 2012-02-19 rsc [0x04] = { 0,0, "MOVW MSW,%e" }, /* word */
454 443d6288 2012-02-19 rsc [0x06] = { 0,0, "MOVW %e,MSW" }, /* word */
455 443d6288 2012-02-19 rsc [0x07] = { 0,0, "INVLPG %e" }, /* or SWAPGS */
458 443d6288 2012-02-19 rsc static Optable optab0F01F8[1]=
460 443d6288 2012-02-19 rsc [0x00] = { 0,0, "SWAPGS" },
467 443d6288 2012-02-19 rsc static Optable optab0FAE[8]=
469 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FXSAVE %e" },
470 443d6288 2012-02-19 rsc [0x01] = { 0,0, "FXRSTOR %e" },
471 443d6288 2012-02-19 rsc [0x02] = { 0,0, "LDMXCSR %e" },
472 443d6288 2012-02-19 rsc [0x03] = { 0,0, "STMXCSR %e" },
473 443d6288 2012-02-19 rsc [0x05] = { 0,0, "LFENCE" },
474 443d6288 2012-02-19 rsc [0x06] = { 0,0, "MFENCE" },
475 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SFENCE" },
481 a84cbb2a 2004-04-19 devnull static Optable optab0FBA[8]=
483 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "BT%S %i,%e" },
484 443d6288 2012-02-19 rsc [0x05] = { Ib,0, "BTS%S %i,%e" },
485 443d6288 2012-02-19 rsc [0x06] = { Ib,0, "BTR%S %i,%e" },
486 443d6288 2012-02-19 rsc [0x07] = { Ib,0, "BTC%S %i,%e" },
489 443d6288 2012-02-19 rsc static Optable optab0F0F[256]=
491 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "PI2FW %m,%M" },
492 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "PI2L %m,%M" },
493 443d6288 2012-02-19 rsc [0x1c] = { 0,0, "PF2IW %m,%M" },
494 443d6288 2012-02-19 rsc [0x1d] = { 0,0, "PF2IL %m,%M" },
495 443d6288 2012-02-19 rsc [0x8a] = { 0,0, "PFNACC %m,%M" },
496 443d6288 2012-02-19 rsc [0x8e] = { 0,0, "PFPNACC %m,%M" },
497 443d6288 2012-02-19 rsc [0x90] = { 0,0, "PFCMPGE %m,%M" },
498 443d6288 2012-02-19 rsc [0x94] = { 0,0, "PFMIN %m,%M" },
499 443d6288 2012-02-19 rsc [0x96] = { 0,0, "PFRCP %m,%M" },
500 443d6288 2012-02-19 rsc [0x97] = { 0,0, "PFRSQRT %m,%M" },
501 443d6288 2012-02-19 rsc [0x9a] = { 0,0, "PFSUB %m,%M" },
502 443d6288 2012-02-19 rsc [0x9e] = { 0,0, "PFADD %m,%M" },
503 443d6288 2012-02-19 rsc [0xa0] = { 0,0, "PFCMPGT %m,%M" },
504 443d6288 2012-02-19 rsc [0xa4] = { 0,0, "PFMAX %m,%M" },
505 443d6288 2012-02-19 rsc [0xa6] = { 0,0, "PFRCPIT1 %m,%M" },
506 443d6288 2012-02-19 rsc [0xa7] = { 0,0, "PFRSQIT1 %m,%M" },
507 443d6288 2012-02-19 rsc [0xaa] = { 0,0, "PFSUBR %m,%M" },
508 443d6288 2012-02-19 rsc [0xae] = { 0,0, "PFACC %m,%M" },
509 443d6288 2012-02-19 rsc [0xb0] = { 0,0, "PFCMPEQ %m,%M" },
510 443d6288 2012-02-19 rsc [0xb4] = { 0,0, "PFMUL %m,%M" },
511 443d6288 2012-02-19 rsc [0xb6] = { 0,0, "PFRCPI2T %m,%M" },
512 443d6288 2012-02-19 rsc [0xb7] = { 0,0, "PMULHRW %m,%M" },
513 443d6288 2012-02-19 rsc [0xbb] = { 0,0, "PSWAPL %m,%M" },
516 443d6288 2012-02-19 rsc static Optable optab0FC7[8]=
518 443d6288 2012-02-19 rsc [0x01] = { 0,0, "CMPXCHG8B %e" },
521 443d6288 2012-02-19 rsc static Optable optab660F71[8]=
523 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "PSRLW %i,%X" },
524 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "PSRAW %i,%X" },
525 443d6288 2012-02-19 rsc [0x06] = { Ib,0, "PSLLW %i,%X" },
528 443d6288 2012-02-19 rsc static Optable optab660F72[8]=
530 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "PSRLL %i,%X" },
531 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "PSRAL %i,%X" },
532 443d6288 2012-02-19 rsc [0x06] = { Ib,0, "PSLLL %i,%X" },
535 443d6288 2012-02-19 rsc static Optable optab660F73[8]=
537 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "PSRLQ %i,%X" },
538 443d6288 2012-02-19 rsc [0x03] = { Ib,0, "PSRLO %i,%X" },
539 443d6288 2012-02-19 rsc [0x06] = { Ib,0, "PSLLQ %i,%X" },
540 443d6288 2012-02-19 rsc [0x07] = { Ib,0, "PSLLO %i,%X" },
543 443d6288 2012-02-19 rsc static Optable optab660F[256]=
545 443d6288 2012-02-19 rsc [0x2B] = { RM,0, "MOVNTPD %x,%e" },
546 443d6288 2012-02-19 rsc [0x2E] = { RM,0, "UCOMISD %x,%X" },
547 443d6288 2012-02-19 rsc [0x2F] = { RM,0, "COMISD %x,%X" },
548 443d6288 2012-02-19 rsc [0x5A] = { RM,0, "CVTPD2PS %x,%X" },
549 443d6288 2012-02-19 rsc [0x5B] = { RM,0, "CVTPS2PL %x,%X" },
550 443d6288 2012-02-19 rsc [0x6A] = { RM,0, "PUNPCKHLQ %x,%X" },
551 443d6288 2012-02-19 rsc [0x6B] = { RM,0, "PACKSSLW %x,%X" },
552 443d6288 2012-02-19 rsc [0x6C] = { RM,0, "PUNPCKLQDQ %x,%X" },
553 443d6288 2012-02-19 rsc [0x6D] = { RM,0, "PUNPCKHQDQ %x,%X" },
554 443d6288 2012-02-19 rsc [0x6E] = { RM,0, "MOV%S %e,%X" },
555 443d6288 2012-02-19 rsc [0x6F] = { RM,0, "MOVO %x,%X" }, /* MOVDQA */
556 443d6288 2012-02-19 rsc [0x70] = { RM,Ib, "PSHUFL %i,%x,%X" },
557 443d6288 2012-02-19 rsc [0x71] = { RMOP,0, optab660F71 },
558 443d6288 2012-02-19 rsc [0x72] = { RMOP,0, optab660F72 },
559 443d6288 2012-02-19 rsc [0x73] = { RMOP,0, optab660F73 },
560 443d6288 2012-02-19 rsc [0x7E] = { RM,0, "MOV%S %X,%e" },
561 443d6288 2012-02-19 rsc [0x7F] = { RM,0, "MOVO %X,%x" },
562 443d6288 2012-02-19 rsc [0xC4] = { RM,Ib, "PINSRW %i,%e,%X" },
563 443d6288 2012-02-19 rsc [0xC5] = { RMR,Ib, "PEXTRW %i,%X,%e" },
564 443d6288 2012-02-19 rsc [0xD4] = { RM,0, "PADDQ %x,%X" },
565 443d6288 2012-02-19 rsc [0xD5] = { RM,0, "PMULLW %x,%X" },
566 443d6288 2012-02-19 rsc [0xD6] = { RM,0, "MOVQ %X,%x" },
567 443d6288 2012-02-19 rsc [0xE6] = { RM,0, "CVTTPD2PL %x,%X" },
568 443d6288 2012-02-19 rsc [0xE7] = { RM,0, "MOVNTO %X,%e" },
569 443d6288 2012-02-19 rsc [0xF7] = { RM,0, "MASKMOVOU %x,%X" },
572 443d6288 2012-02-19 rsc static Optable optabF20F[256]=
574 443d6288 2012-02-19 rsc [0x10] = { RM,0, "MOVSD %x,%X" },
575 443d6288 2012-02-19 rsc [0x11] = { RM,0, "MOVSD %X,%x" },
576 443d6288 2012-02-19 rsc [0x2A] = { RM,0, "CVTS%S2SD %e,%X" },
577 443d6288 2012-02-19 rsc [0x2C] = { RM,0, "CVTTSD2S%S %x,%r" },
578 443d6288 2012-02-19 rsc [0x2D] = { RM,0, "CVTSD2S%S %x,%r" },
579 443d6288 2012-02-19 rsc [0x5A] = { RM,0, "CVTSD2SS %x,%X" },
580 443d6288 2012-02-19 rsc [0x6F] = { RM,0, "MOVOU %x,%X" },
581 443d6288 2012-02-19 rsc [0x70] = { RM,Ib, "PSHUFLW %i,%x,%X" },
582 443d6288 2012-02-19 rsc [0x7F] = { RM,0, "MOVOU %X,%x" },
583 443d6288 2012-02-19 rsc [0xD6] = { RM,0, "MOVQOZX %M,%X" },
584 443d6288 2012-02-19 rsc [0xE6] = { RM,0, "CVTPD2PL %x,%X" },
587 443d6288 2012-02-19 rsc static Optable optabF30F[256]=
589 443d6288 2012-02-19 rsc [0x10] = { RM,0, "MOVSS %x,%X" },
590 443d6288 2012-02-19 rsc [0x11] = { RM,0, "MOVSS %X,%x" },
591 443d6288 2012-02-19 rsc [0x2A] = { RM,0, "CVTS%S2SS %e,%X" },
592 443d6288 2012-02-19 rsc [0x2C] = { RM,0, "CVTTSS2S%S %x,%r" },
593 443d6288 2012-02-19 rsc [0x2D] = { RM,0, "CVTSS2S%S %x,%r" },
594 443d6288 2012-02-19 rsc [0x5A] = { RM,0, "CVTSS2SD %x,%X" },
595 443d6288 2012-02-19 rsc [0x5B] = { RM,0, "CVTTPS2PL %x,%X" },
596 443d6288 2012-02-19 rsc [0x6F] = { RM,0, "MOVOU %x,%X" },
597 443d6288 2012-02-19 rsc [0x70] = { RM,Ib, "PSHUFHW %i,%x,%X" },
598 443d6288 2012-02-19 rsc [0x7E] = { RM,0, "MOVQOZX %x,%X" },
599 443d6288 2012-02-19 rsc [0x7F] = { RM,0, "MOVOU %X,%x" },
600 443d6288 2012-02-19 rsc [0xD6] = { RM,0, "MOVQOZX %m*,%X" },
601 443d6288 2012-02-19 rsc [0xE6] = { RM,0, "CVTPL2PD %x,%X" },
604 a84cbb2a 2004-04-19 devnull static Optable optab0F[256]=
606 443d6288 2012-02-19 rsc [0x00] = { RMOP,0, optab0F00 },
607 443d6288 2012-02-19 rsc [0x01] = { RMOP,0, optab0F01 },
608 443d6288 2012-02-19 rsc [0x02] = { RM,0, "LAR %e,%r" },
609 443d6288 2012-02-19 rsc [0x03] = { RM,0, "LSL %e,%r" },
610 443d6288 2012-02-19 rsc [0x05] = { 0,0, "SYSCALL" },
611 443d6288 2012-02-19 rsc [0x06] = { 0,0, "CLTS" },
612 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SYSRET" },
613 443d6288 2012-02-19 rsc [0x08] = { 0,0, "INVD" },
614 443d6288 2012-02-19 rsc [0x09] = { 0,0, "WBINVD" },
615 443d6288 2012-02-19 rsc [0x0B] = { 0,0, "UD2" },
616 443d6288 2012-02-19 rsc [0x0F] = { RM,AUX, optab0F0F }, /* 3DNow! */
617 443d6288 2012-02-19 rsc [0x10] = { RM,0, "MOVU%s %x,%X" },
618 443d6288 2012-02-19 rsc [0x11] = { RM,0, "MOVU%s %X,%x" },
619 443d6288 2012-02-19 rsc [0x12] = { RM,0, "MOV[H]L%s %x,%X" }, /* TO DO: H if source is XMM */
620 443d6288 2012-02-19 rsc [0x13] = { RM,0, "MOVL%s %X,%e" },
621 443d6288 2012-02-19 rsc [0x14] = { RM,0, "UNPCKL%s %x,%X" },
622 443d6288 2012-02-19 rsc [0x15] = { RM,0, "UNPCKH%s %x,%X" },
623 443d6288 2012-02-19 rsc [0x16] = { RM,0, "MOV[L]H%s %x,%X" }, /* TO DO: L if source is XMM */
624 443d6288 2012-02-19 rsc [0x17] = { RM,0, "MOVH%s %X,%x" },
625 443d6288 2012-02-19 rsc [0x20] = { RMR,0, "MOVL %C,%e" },
626 443d6288 2012-02-19 rsc [0x21] = { RMR,0, "MOVL %D,%e" },
627 443d6288 2012-02-19 rsc [0x22] = { RMR,0, "MOVL %e,%C" },
628 443d6288 2012-02-19 rsc [0x23] = { RMR,0, "MOVL %e,%D" },
629 443d6288 2012-02-19 rsc [0x24] = { RMR,0, "MOVL %T,%e" },
630 443d6288 2012-02-19 rsc [0x26] = { RMR,0, "MOVL %e,%T" },
631 443d6288 2012-02-19 rsc [0x28] = { RM,0, "MOVA%s %x,%X" },
632 443d6288 2012-02-19 rsc [0x29] = { RM,0, "MOVA%s %X,%x" },
633 443d6288 2012-02-19 rsc [0x2A] = { RM,0, "CVTPL2%s %m*,%X" },
634 443d6288 2012-02-19 rsc [0x2B] = { RM,0, "MOVNT%s %X,%e" },
635 443d6288 2012-02-19 rsc [0x2C] = { RM,0, "CVTT%s2PL %x,%M" },
636 443d6288 2012-02-19 rsc [0x2D] = { RM,0, "CVT%s2PL %x,%M" },
637 443d6288 2012-02-19 rsc [0x2E] = { RM,0, "UCOMISS %x,%X" },
638 443d6288 2012-02-19 rsc [0x2F] = { RM,0, "COMISS %x,%X" },
639 443d6288 2012-02-19 rsc [0x30] = { 0,0, "WRMSR" },
640 443d6288 2012-02-19 rsc [0x31] = { 0,0, "RDTSC" },
641 443d6288 2012-02-19 rsc [0x32] = { 0,0, "RDMSR" },
642 443d6288 2012-02-19 rsc [0x33] = { 0,0, "RDPMC" },
643 443d6288 2012-02-19 rsc [0x42] = { RM,0, "CMOVC %e,%r" }, /* CF */
644 443d6288 2012-02-19 rsc [0x43] = { RM,0, "CMOVNC %e,%r" }, /* ¬ CF */
645 443d6288 2012-02-19 rsc [0x44] = { RM,0, "CMOVZ %e,%r" }, /* ZF */
646 443d6288 2012-02-19 rsc [0x45] = { RM,0, "CMOVNZ %e,%r" }, /* ¬ ZF */
647 443d6288 2012-02-19 rsc [0x46] = { RM,0, "CMOVBE %e,%r" }, /* CF ∨ ZF */
648 443d6288 2012-02-19 rsc [0x47] = { RM,0, "CMOVA %e,%r" }, /* ¬CF ∧ ¬ZF */
649 443d6288 2012-02-19 rsc [0x48] = { RM,0, "CMOVS %e,%r" }, /* SF */
650 443d6288 2012-02-19 rsc [0x49] = { RM,0, "CMOVNS %e,%r" }, /* ¬ SF */
651 443d6288 2012-02-19 rsc [0x4A] = { RM,0, "CMOVP %e,%r" }, /* PF */
652 443d6288 2012-02-19 rsc [0x4B] = { RM,0, "CMOVNP %e,%r" }, /* ¬ PF */
653 443d6288 2012-02-19 rsc [0x4C] = { RM,0, "CMOVLT %e,%r" }, /* LT ≡ OF ≠SF */
654 443d6288 2012-02-19 rsc [0x4D] = { RM,0, "CMOVGE %e,%r" }, /* GE ≡ ZF ∨ SF */
655 443d6288 2012-02-19 rsc [0x4E] = { RM,0, "CMOVLE %e,%r" }, /* LE ≡ ZF ∨ LT */
656 443d6288 2012-02-19 rsc [0x4F] = { RM,0, "CMOVGT %e,%r" }, /* GT ≡ ¬ZF ∧ GE */
657 443d6288 2012-02-19 rsc [0x50] = { RM,0, "MOVMSK%s %X,%r" }, /* TO DO: check */
658 443d6288 2012-02-19 rsc [0x51] = { RM,0, "SQRT%s %x,%X" },
659 443d6288 2012-02-19 rsc [0x52] = { RM,0, "RSQRT%s %x,%X" },
660 443d6288 2012-02-19 rsc [0x53] = { RM,0, "RCP%s %x,%X" },
661 443d6288 2012-02-19 rsc [0x54] = { RM,0, "AND%s %x,%X" },
662 443d6288 2012-02-19 rsc [0x55] = { RM,0, "ANDN%s %x,%X" },
663 443d6288 2012-02-19 rsc [0x56] = { RM,0, "OR%s %x,%X" }, /* TO DO: S/D */
664 443d6288 2012-02-19 rsc [0x57] = { RM,0, "XOR%s %x,%X" }, /* S/D */
665 443d6288 2012-02-19 rsc [0x58] = { RM,0, "ADD%s %x,%X" }, /* S/P S/D */
666 443d6288 2012-02-19 rsc [0x59] = { RM,0, "MUL%s %x,%X" },
667 443d6288 2012-02-19 rsc [0x5A] = { RM,0, "CVTPS2PD %x,%X" },
668 443d6288 2012-02-19 rsc [0x5B] = { RM,0, "CVTPL2PS %x,%X" },
669 443d6288 2012-02-19 rsc [0x5C] = { RM,0, "SUB%s %x,%X" },
670 443d6288 2012-02-19 rsc [0x5D] = { RM,0, "MIN%s %x,%X" },
671 443d6288 2012-02-19 rsc [0x5E] = { RM,0, "DIV%s %x,%X" }, /* TO DO: S/P S/D */
672 443d6288 2012-02-19 rsc [0x5F] = { RM,0, "MAX%s %x,%X" },
673 443d6288 2012-02-19 rsc [0x60] = { RM,0, "PUNPCKLBW %m,%M" },
674 443d6288 2012-02-19 rsc [0x61] = { RM,0, "PUNPCKLWL %m,%M" },
675 443d6288 2012-02-19 rsc [0x62] = { RM,0, "PUNPCKLLQ %m,%M" },
676 443d6288 2012-02-19 rsc [0x63] = { RM,0, "PACKSSWB %m,%M" },
677 443d6288 2012-02-19 rsc [0x64] = { RM,0, "PCMPGTB %m,%M" },
678 443d6288 2012-02-19 rsc [0x65] = { RM,0, "PCMPGTW %m,%M" },
679 443d6288 2012-02-19 rsc [0x66] = { RM,0, "PCMPGTL %m,%M" },
680 443d6288 2012-02-19 rsc [0x67] = { RM,0, "PACKUSWB %m,%M" },
681 443d6288 2012-02-19 rsc [0x68] = { RM,0, "PUNPCKHBW %m,%M" },
682 443d6288 2012-02-19 rsc [0x69] = { RM,0, "PUNPCKHWL %m,%M" },
683 443d6288 2012-02-19 rsc [0x6A] = { RM,0, "PUNPCKHLQ %m,%M" },
684 443d6288 2012-02-19 rsc [0x6B] = { RM,0, "PACKSSLW %m,%M" },
685 443d6288 2012-02-19 rsc [0x6E] = { RM,0, "MOV%S %e,%M" },
686 443d6288 2012-02-19 rsc [0x6F] = { RM,0, "MOVQ %m,%M" },
687 443d6288 2012-02-19 rsc [0x70] = { RM,Ib, "PSHUFW %i,%m,%M" },
688 443d6288 2012-02-19 rsc [0x74] = { RM,0, "PCMPEQB %m,%M" },
689 443d6288 2012-02-19 rsc [0x75] = { RM,0, "PCMPEQW %m,%M" },
690 443d6288 2012-02-19 rsc [0x76] = { RM,0, "PCMPEQL %m,%M" },
691 443d6288 2012-02-19 rsc [0x77] = { 0,0, "EMMS" },
692 443d6288 2012-02-19 rsc [0x7E] = { RM,0, "MOV%S %M,%e" },
693 443d6288 2012-02-19 rsc [0x7F] = { RM,0, "MOVQ %M,%m" },
694 443d6288 2012-02-19 rsc [0xAE] = { RMOP,0, optab0FAE },
695 443d6288 2012-02-19 rsc [0xAA] = { 0,0, "RSM" },
696 443d6288 2012-02-19 rsc [0xB0] = { RM,0, "CMPXCHGB %r,%e" },
697 443d6288 2012-02-19 rsc [0xB1] = { RM,0, "CMPXCHG%S %r,%e" },
698 443d6288 2012-02-19 rsc [0xC0] = { RMB,0, "XADDB %r,%e" },
699 443d6288 2012-02-19 rsc [0xC1] = { RM,0, "XADD%S %r,%e" },
700 443d6288 2012-02-19 rsc [0xC2] = { RM,Ib, "CMP%s %x,%X,%#i" },
701 443d6288 2012-02-19 rsc [0xC3] = { RM,0, "MOVNTI%S %r,%e" },
702 443d6288 2012-02-19 rsc [0xC6] = { RM,Ib, "SHUF%s %i,%x,%X" },
703 443d6288 2012-02-19 rsc [0xC8] = { 0,0, "BSWAP AX" },
704 443d6288 2012-02-19 rsc [0xC9] = { 0,0, "BSWAP CX" },
705 443d6288 2012-02-19 rsc [0xCA] = { 0,0, "BSWAP DX" },
706 443d6288 2012-02-19 rsc [0xCB] = { 0,0, "BSWAP BX" },
707 443d6288 2012-02-19 rsc [0xCC] = { 0,0, "BSWAP SP" },
708 443d6288 2012-02-19 rsc [0xCD] = { 0,0, "BSWAP BP" },
709 443d6288 2012-02-19 rsc [0xCE] = { 0,0, "BSWAP SI" },
710 443d6288 2012-02-19 rsc [0xCF] = { 0,0, "BSWAP DI" },
711 443d6288 2012-02-19 rsc [0xD1] = { RM,0, "PSRLW %m,%M" },
712 443d6288 2012-02-19 rsc [0xD2] = { RM,0, "PSRLL %m,%M" },
713 443d6288 2012-02-19 rsc [0xD3] = { RM,0, "PSRLQ %m,%M" },
714 443d6288 2012-02-19 rsc [0xD5] = { RM,0, "PMULLW %m,%M" },
715 443d6288 2012-02-19 rsc [0xD6] = { RM,0, "MOVQOZX %m*,%X" },
716 443d6288 2012-02-19 rsc [0xD7] = { RM,0, "PMOVMSKB %m,%r" },
717 443d6288 2012-02-19 rsc [0xD8] = { RM,0, "PSUBUSB %m,%M" },
718 443d6288 2012-02-19 rsc [0xD9] = { RM,0, "PSUBUSW %m,%M" },
719 443d6288 2012-02-19 rsc [0xDA] = { RM,0, "PMINUB %m,%M" },
720 443d6288 2012-02-19 rsc [0xDB] = { RM,0, "PAND %m,%M" },
721 443d6288 2012-02-19 rsc [0xDC] = { RM,0, "PADDUSB %m,%M" },
722 443d6288 2012-02-19 rsc [0xDD] = { RM,0, "PADDUSW %m,%M" },
723 443d6288 2012-02-19 rsc [0xDE] = { RM,0, "PMAXUB %m,%M" },
724 443d6288 2012-02-19 rsc [0xDF] = { RM,0, "PANDN %m,%M" },
725 443d6288 2012-02-19 rsc [0xE0] = { RM,0, "PAVGB %m,%M" },
726 443d6288 2012-02-19 rsc [0xE1] = { RM,0, "PSRAW %m,%M" },
727 443d6288 2012-02-19 rsc [0xE2] = { RM,0, "PSRAL %m,%M" },
728 443d6288 2012-02-19 rsc [0xE3] = { RM,0, "PAVGW %m,%M" },
729 443d6288 2012-02-19 rsc [0xE4] = { RM,0, "PMULHUW %m,%M" },
730 443d6288 2012-02-19 rsc [0xE5] = { RM,0, "PMULHW %m,%M" },
731 443d6288 2012-02-19 rsc [0xE7] = { RM,0, "MOVNTQ %M,%e" },
732 443d6288 2012-02-19 rsc [0xE8] = { RM,0, "PSUBSB %m,%M" },
733 443d6288 2012-02-19 rsc [0xE9] = { RM,0, "PSUBSW %m,%M" },
734 443d6288 2012-02-19 rsc [0xEA] = { RM,0, "PMINSW %m,%M" },
735 443d6288 2012-02-19 rsc [0xEB] = { RM,0, "POR %m,%M" },
736 443d6288 2012-02-19 rsc [0xEC] = { RM,0, "PADDSB %m,%M" },
737 443d6288 2012-02-19 rsc [0xED] = { RM,0, "PADDSW %m,%M" },
738 443d6288 2012-02-19 rsc [0xEE] = { RM,0, "PMAXSW %m,%M" },
739 443d6288 2012-02-19 rsc [0xEF] = { RM,0, "PXOR %m,%M" },
740 443d6288 2012-02-19 rsc [0xF1] = { RM,0, "PSLLW %m,%M" },
741 443d6288 2012-02-19 rsc [0xF2] = { RM,0, "PSLLL %m,%M" },
742 443d6288 2012-02-19 rsc [0xF3] = { RM,0, "PSLLQ %m,%M" },
743 443d6288 2012-02-19 rsc [0xF4] = { RM,0, "PMULULQ %m,%M" },
744 443d6288 2012-02-19 rsc [0xF5] = { RM,0, "PMADDWL %m,%M" },
745 443d6288 2012-02-19 rsc [0xF6] = { RM,0, "PSADBW %m,%M" },
746 443d6288 2012-02-19 rsc [0xF7] = { RMR,0, "MASKMOVQ %m,%M" },
747 443d6288 2012-02-19 rsc [0xF8] = { RM,0, "PSUBB %m,%M" },
748 443d6288 2012-02-19 rsc [0xF9] = { RM,0, "PSUBW %m,%M" },
749 443d6288 2012-02-19 rsc [0xFA] = { RM,0, "PSUBL %m,%M" },
750 443d6288 2012-02-19 rsc [0xFC] = { RM,0, "PADDB %m,%M" },
751 443d6288 2012-02-19 rsc [0xFD] = { RM,0, "PADDW %m,%M" },
752 443d6288 2012-02-19 rsc [0xFE] = { RM,0, "PADDL %m,%M" },
754 443d6288 2012-02-19 rsc [0x80] = { Iwds,0, "JOS %p" },
755 443d6288 2012-02-19 rsc [0x81] = { Iwds,0, "JOC %p" },
756 443d6288 2012-02-19 rsc [0x82] = { Iwds,0, "JCS %p" },
757 443d6288 2012-02-19 rsc [0x83] = { Iwds,0, "JCC %p" },
758 443d6288 2012-02-19 rsc [0x84] = { Iwds,0, "JEQ %p" },
759 443d6288 2012-02-19 rsc [0x85] = { Iwds,0, "JNE %p" },
760 443d6288 2012-02-19 rsc [0x86] = { Iwds,0, "JLS %p" },
761 443d6288 2012-02-19 rsc [0x87] = { Iwds,0, "JHI %p" },
762 443d6288 2012-02-19 rsc [0x88] = { Iwds,0, "JMI %p" },
763 443d6288 2012-02-19 rsc [0x89] = { Iwds,0, "JPL %p" },
764 443d6288 2012-02-19 rsc [0x8a] = { Iwds,0, "JPS %p" },
765 443d6288 2012-02-19 rsc [0x8b] = { Iwds,0, "JPC %p" },
766 443d6288 2012-02-19 rsc [0x8c] = { Iwds,0, "JLT %p" },
767 443d6288 2012-02-19 rsc [0x8d] = { Iwds,0, "JGE %p" },
768 443d6288 2012-02-19 rsc [0x8e] = { Iwds,0, "JLE %p" },
769 443d6288 2012-02-19 rsc [0x8f] = { Iwds,0, "JGT %p" },
770 443d6288 2012-02-19 rsc [0x90] = { RMB,0, "SETOS %e" },
771 443d6288 2012-02-19 rsc [0x91] = { RMB,0, "SETOC %e" },
772 443d6288 2012-02-19 rsc [0x92] = { RMB,0, "SETCS %e" },
773 443d6288 2012-02-19 rsc [0x93] = { RMB,0, "SETCC %e" },
774 443d6288 2012-02-19 rsc [0x94] = { RMB,0, "SETEQ %e" },
775 443d6288 2012-02-19 rsc [0x95] = { RMB,0, "SETNE %e" },
776 443d6288 2012-02-19 rsc [0x96] = { RMB,0, "SETLS %e" },
777 443d6288 2012-02-19 rsc [0x97] = { RMB,0, "SETHI %e" },
778 443d6288 2012-02-19 rsc [0x98] = { RMB,0, "SETMI %e" },
779 443d6288 2012-02-19 rsc [0x99] = { RMB,0, "SETPL %e" },
780 443d6288 2012-02-19 rsc [0x9a] = { RMB,0, "SETPS %e" },
781 443d6288 2012-02-19 rsc [0x9b] = { RMB,0, "SETPC %e" },
782 443d6288 2012-02-19 rsc [0x9c] = { RMB,0, "SETLT %e" },
783 443d6288 2012-02-19 rsc [0x9d] = { RMB,0, "SETGE %e" },
784 443d6288 2012-02-19 rsc [0x9e] = { RMB,0, "SETLE %e" },
785 443d6288 2012-02-19 rsc [0x9f] = { RMB,0, "SETGT %e" },
786 443d6288 2012-02-19 rsc [0xa0] = { 0,0, "PUSHL FS" },
787 443d6288 2012-02-19 rsc [0xa1] = { 0,0, "POPL FS" },
788 443d6288 2012-02-19 rsc [0xa2] = { 0,0, "CPUID" },
789 443d6288 2012-02-19 rsc [0xa3] = { RM,0, "BT%S %r,%e" },
790 443d6288 2012-02-19 rsc [0xa4] = { RM,Ib, "SHLD%S %r,%i,%e" },
791 443d6288 2012-02-19 rsc [0xa5] = { RM,0, "SHLD%S %r,CL,%e" },
792 443d6288 2012-02-19 rsc [0xa8] = { 0,0, "PUSHL GS" },
793 443d6288 2012-02-19 rsc [0xa9] = { 0,0, "POPL GS" },
794 443d6288 2012-02-19 rsc [0xab] = { RM,0, "BTS%S %r,%e" },
795 443d6288 2012-02-19 rsc [0xac] = { RM,Ib, "SHRD%S %r,%i,%e" },
796 443d6288 2012-02-19 rsc [0xad] = { RM,0, "SHRD%S %r,CL,%e" },
797 443d6288 2012-02-19 rsc [0xaf] = { RM,0, "IMUL%S %e,%r" },
798 443d6288 2012-02-19 rsc [0xb2] = { RMM,0, "LSS %e,%r" },
799 443d6288 2012-02-19 rsc [0xb3] = { RM,0, "BTR%S %r,%e" },
800 443d6288 2012-02-19 rsc [0xb4] = { RMM,0, "LFS %e,%r" },
801 443d6288 2012-02-19 rsc [0xb5] = { RMM,0, "LGS %e,%r" },
802 443d6288 2012-02-19 rsc [0xb6] = { RMB,0, "MOVBZX %e,%R" },
803 443d6288 2012-02-19 rsc [0xb7] = { RM,0, "MOVWZX %e,%R" },
804 443d6288 2012-02-19 rsc [0xba] = { RMOP,0, optab0FBA },
805 443d6288 2012-02-19 rsc [0xbb] = { RM,0, "BTC%S %e,%r" },
806 443d6288 2012-02-19 rsc [0xbc] = { RM,0, "BSF%S %e,%r" },
807 443d6288 2012-02-19 rsc [0xbd] = { RM,0, "BSR%S %e,%r" },
808 443d6288 2012-02-19 rsc [0xbe] = { RMB,0, "MOVBSX %e,%R" },
809 443d6288 2012-02-19 rsc [0xbf] = { RM,0, "MOVWSX %e,%R" },
810 443d6288 2012-02-19 rsc [0xc7] = { RMOP,0, optab0FC7 },
813 a84cbb2a 2004-04-19 devnull static Optable optab80[8]=
815 443d6288 2012-02-19 rsc [0x00] = { Ib,0, "ADDB %i,%e" },
816 443d6288 2012-02-19 rsc [0x01] = { Ib,0, "ORB %i,%e" },
817 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "ADCB %i,%e" },
818 443d6288 2012-02-19 rsc [0x03] = { Ib,0, "SBBB %i,%e" },
819 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "ANDB %i,%e" },
820 443d6288 2012-02-19 rsc [0x05] = { Ib,0, "SUBB %i,%e" },
821 443d6288 2012-02-19 rsc [0x06] = { Ib,0, "XORB %i,%e" },
822 443d6288 2012-02-19 rsc [0x07] = { Ib,0, "CMPB %e,%i" },
825 a84cbb2a 2004-04-19 devnull static Optable optab81[8]=
827 443d6288 2012-02-19 rsc [0x00] = { Iwd,0, "ADD%S %i,%e" },
828 443d6288 2012-02-19 rsc [0x01] = { Iwd,0, "OR%S %i,%e" },
829 443d6288 2012-02-19 rsc [0x02] = { Iwd,0, "ADC%S %i,%e" },
830 443d6288 2012-02-19 rsc [0x03] = { Iwd,0, "SBB%S %i,%e" },
831 443d6288 2012-02-19 rsc [0x04] = { Iwd,0, "AND%S %i,%e" },
832 443d6288 2012-02-19 rsc [0x05] = { Iwd,0, "SUB%S %i,%e" },
833 443d6288 2012-02-19 rsc [0x06] = { Iwd,0, "XOR%S %i,%e" },
834 443d6288 2012-02-19 rsc [0x07] = { Iwd,0, "CMP%S %e,%i" },
837 a84cbb2a 2004-04-19 devnull static Optable optab83[8]=
839 443d6288 2012-02-19 rsc [0x00] = { Ibs,0, "ADD%S %i,%e" },
840 443d6288 2012-02-19 rsc [0x01] = { Ibs,0, "OR%S %i,%e" },
841 443d6288 2012-02-19 rsc [0x02] = { Ibs,0, "ADC%S %i,%e" },
842 443d6288 2012-02-19 rsc [0x03] = { Ibs,0, "SBB%S %i,%e" },
843 443d6288 2012-02-19 rsc [0x04] = { Ibs,0, "AND%S %i,%e" },
844 443d6288 2012-02-19 rsc [0x05] = { Ibs,0, "SUB%S %i,%e" },
845 443d6288 2012-02-19 rsc [0x06] = { Ibs,0, "XOR%S %i,%e" },
846 443d6288 2012-02-19 rsc [0x07] = { Ibs,0, "CMP%S %e,%i" },
849 a84cbb2a 2004-04-19 devnull static Optable optabC0[8] =
851 443d6288 2012-02-19 rsc [0x00] = { Ib,0, "ROLB %i,%e" },
852 443d6288 2012-02-19 rsc [0x01] = { Ib,0, "RORB %i,%e" },
853 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "RCLB %i,%e" },
854 443d6288 2012-02-19 rsc [0x03] = { Ib,0, "RCRB %i,%e" },
855 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "SHLB %i,%e" },
856 443d6288 2012-02-19 rsc [0x05] = { Ib,0, "SHRB %i,%e" },
857 443d6288 2012-02-19 rsc [0x07] = { Ib,0, "SARB %i,%e" },
860 a84cbb2a 2004-04-19 devnull static Optable optabC1[8] =
862 443d6288 2012-02-19 rsc [0x00] = { Ib,0, "ROL%S %i,%e" },
863 443d6288 2012-02-19 rsc [0x01] = { Ib,0, "ROR%S %i,%e" },
864 443d6288 2012-02-19 rsc [0x02] = { Ib,0, "RCL%S %i,%e" },
865 443d6288 2012-02-19 rsc [0x03] = { Ib,0, "RCR%S %i,%e" },
866 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "SHL%S %i,%e" },
867 443d6288 2012-02-19 rsc [0x05] = { Ib,0, "SHR%S %i,%e" },
868 443d6288 2012-02-19 rsc [0x07] = { Ib,0, "SAR%S %i,%e" },
871 a84cbb2a 2004-04-19 devnull static Optable optabD0[8] =
873 443d6288 2012-02-19 rsc [0x00] = { 0,0, "ROLB %e" },
874 443d6288 2012-02-19 rsc [0x01] = { 0,0, "RORB %e" },
875 443d6288 2012-02-19 rsc [0x02] = { 0,0, "RCLB %e" },
876 443d6288 2012-02-19 rsc [0x03] = { 0,0, "RCRB %e" },
877 443d6288 2012-02-19 rsc [0x04] = { 0,0, "SHLB %e" },
878 443d6288 2012-02-19 rsc [0x05] = { 0,0, "SHRB %e" },
879 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SARB %e" },
882 a84cbb2a 2004-04-19 devnull static Optable optabD1[8] =
884 443d6288 2012-02-19 rsc [0x00] = { 0,0, "ROL%S %e" },
885 443d6288 2012-02-19 rsc [0x01] = { 0,0, "ROR%S %e" },
886 443d6288 2012-02-19 rsc [0x02] = { 0,0, "RCL%S %e" },
887 443d6288 2012-02-19 rsc [0x03] = { 0,0, "RCR%S %e" },
888 443d6288 2012-02-19 rsc [0x04] = { 0,0, "SHL%S %e" },
889 443d6288 2012-02-19 rsc [0x05] = { 0,0, "SHR%S %e" },
890 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SAR%S %e" },
893 a84cbb2a 2004-04-19 devnull static Optable optabD2[8] =
895 443d6288 2012-02-19 rsc [0x00] = { 0,0, "ROLB CL,%e" },
896 443d6288 2012-02-19 rsc [0x01] = { 0,0, "RORB CL,%e" },
897 443d6288 2012-02-19 rsc [0x02] = { 0,0, "RCLB CL,%e" },
898 443d6288 2012-02-19 rsc [0x03] = { 0,0, "RCRB CL,%e" },
899 443d6288 2012-02-19 rsc [0x04] = { 0,0, "SHLB CL,%e" },
900 443d6288 2012-02-19 rsc [0x05] = { 0,0, "SHRB CL,%e" },
901 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SARB CL,%e" },
904 a84cbb2a 2004-04-19 devnull static Optable optabD3[8] =
906 443d6288 2012-02-19 rsc [0x00] = { 0,0, "ROL%S CL,%e" },
907 443d6288 2012-02-19 rsc [0x01] = { 0,0, "ROR%S CL,%e" },
908 443d6288 2012-02-19 rsc [0x02] = { 0,0, "RCL%S CL,%e" },
909 443d6288 2012-02-19 rsc [0x03] = { 0,0, "RCR%S CL,%e" },
910 443d6288 2012-02-19 rsc [0x04] = { 0,0, "SHL%S CL,%e" },
911 443d6288 2012-02-19 rsc [0x05] = { 0,0, "SHR%S CL,%e" },
912 443d6288 2012-02-19 rsc [0x07] = { 0,0, "SAR%S CL,%e" },
915 a84cbb2a 2004-04-19 devnull static Optable optabD8[8+8] =
917 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FADDF %e,F0" },
918 443d6288 2012-02-19 rsc [0x01] = { 0,0, "FMULF %e,F0" },
919 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FCOMF %e,F0" },
920 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FCOMFP %e,F0" },
921 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FSUBF %e,F0" },
922 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FSUBRF %e,F0" },
923 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FDIVF %e,F0" },
924 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FDIVRF %e,F0" },
925 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FADDD %f,F0" },
926 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FMULD %f,F0" },
927 443d6288 2012-02-19 rsc [0x0a] = { 0,0, "FCOMD %f,F0" },
928 443d6288 2012-02-19 rsc [0x0b] = { 0,0, "FCOMPD %f,F0" },
929 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FSUBD %f,F0" },
930 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FSUBRD %f,F0" },
931 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FDIVD %f,F0" },
932 443d6288 2012-02-19 rsc [0x0f] = { 0,0, "FDIVRD %f,F0" },
935 443d6288 2012-02-19 rsc * optabD9 and optabDB use the following encoding:
936 a84cbb2a 2004-04-19 devnull * if (0 <= modrm <= 2) instruction = optabDx[modrm&0x07];
937 a84cbb2a 2004-04-19 devnull * else instruction = optabDx[(modrm&0x3f)+8];
939 a84cbb2a 2004-04-19 devnull * the instructions for MOD == 3, follow the 8 instructions
940 a84cbb2a 2004-04-19 devnull * for the other MOD values stored at the front of the table.
942 a84cbb2a 2004-04-19 devnull static Optable optabD9[64+8] =
944 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FMOVF %e,F0" },
945 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FMOVF F0,%e" },
946 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FMOVFP F0,%e" },
947 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FLDENV%S %e" },
948 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FLDCW %e" },
949 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FSTENV%S %e" },
950 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FSTCW %e" },
951 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FMOVD F0,F0" }, /* Mod R/M = 11xx xxxx*/
952 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FMOVD F1,F0" },
953 443d6288 2012-02-19 rsc [0x0a] = { 0,0, "FMOVD F2,F0" },
954 443d6288 2012-02-19 rsc [0x0b] = { 0,0, "FMOVD F3,F0" },
955 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FMOVD F4,F0" },
956 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FMOVD F5,F0" },
957 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FMOVD F6,F0" },
958 443d6288 2012-02-19 rsc [0x0f] = { 0,0, "FMOVD F7,F0" },
959 443d6288 2012-02-19 rsc [0x10] = { 0,0, "FXCHD F0,F0" },
960 443d6288 2012-02-19 rsc [0x11] = { 0,0, "FXCHD F1,F0" },
961 443d6288 2012-02-19 rsc [0x12] = { 0,0, "FXCHD F2,F0" },
962 443d6288 2012-02-19 rsc [0x13] = { 0,0, "FXCHD F3,F0" },
963 443d6288 2012-02-19 rsc [0x14] = { 0,0, "FXCHD F4,F0" },
964 443d6288 2012-02-19 rsc [0x15] = { 0,0, "FXCHD F5,F0" },
965 443d6288 2012-02-19 rsc [0x16] = { 0,0, "FXCHD F6,F0" },
966 443d6288 2012-02-19 rsc [0x17] = { 0,0, "FXCHD F7,F0" },
967 443d6288 2012-02-19 rsc [0x18] = { 0,0, "FNOP" },
968 443d6288 2012-02-19 rsc [0x28] = { 0,0, "FCHS" },
969 443d6288 2012-02-19 rsc [0x29] = { 0,0, "FABS" },
970 443d6288 2012-02-19 rsc [0x2c] = { 0,0, "FTST" },
971 443d6288 2012-02-19 rsc [0x2d] = { 0,0, "FXAM" },
972 443d6288 2012-02-19 rsc [0x30] = { 0,0, "FLD1" },
973 443d6288 2012-02-19 rsc [0x31] = { 0,0, "FLDL2T" },
974 443d6288 2012-02-19 rsc [0x32] = { 0,0, "FLDL2E" },
975 443d6288 2012-02-19 rsc [0x33] = { 0,0, "FLDPI" },
976 443d6288 2012-02-19 rsc [0x34] = { 0,0, "FLDLG2" },
977 443d6288 2012-02-19 rsc [0x35] = { 0,0, "FLDLN2" },
978 443d6288 2012-02-19 rsc [0x36] = { 0,0, "FLDZ" },
979 443d6288 2012-02-19 rsc [0x38] = { 0,0, "F2XM1" },
980 443d6288 2012-02-19 rsc [0x39] = { 0,0, "FYL2X" },
981 443d6288 2012-02-19 rsc [0x3a] = { 0,0, "FPTAN" },
982 443d6288 2012-02-19 rsc [0x3b] = { 0,0, "FPATAN" },
983 443d6288 2012-02-19 rsc [0x3c] = { 0,0, "FXTRACT" },
984 443d6288 2012-02-19 rsc [0x3d] = { 0,0, "FPREM1" },
985 443d6288 2012-02-19 rsc [0x3e] = { 0,0, "FDECSTP" },
986 443d6288 2012-02-19 rsc [0x3f] = { 0,0, "FNCSTP" },
987 443d6288 2012-02-19 rsc [0x40] = { 0,0, "FPREM" },
988 443d6288 2012-02-19 rsc [0x41] = { 0,0, "FYL2XP1" },
989 443d6288 2012-02-19 rsc [0x42] = { 0,0, "FSQRT" },
990 443d6288 2012-02-19 rsc [0x43] = { 0,0, "FSINCOS" },
991 443d6288 2012-02-19 rsc [0x44] = { 0,0, "FRNDINT" },
992 443d6288 2012-02-19 rsc [0x45] = { 0,0, "FSCALE" },
993 443d6288 2012-02-19 rsc [0x46] = { 0,0, "FSIN" },
994 443d6288 2012-02-19 rsc [0x47] = { 0,0, "FCOS" },
997 a84cbb2a 2004-04-19 devnull static Optable optabDA[8+8] =
999 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FADDL %e,F0" },
1000 443d6288 2012-02-19 rsc [0x01] = { 0,0, "FMULL %e,F0" },
1001 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FCOML %e,F0" },
1002 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FCOMLP %e,F0" },
1003 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FSUBL %e,F0" },
1004 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FSUBRL %e,F0" },
1005 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FDIVL %e,F0" },
1006 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FDIVRL %e,F0" },
1007 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FCMOVCS %f,F0" },
1008 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FCMOVEQ %f,F0" },
1009 443d6288 2012-02-19 rsc [0x0a] = { 0,0, "FCMOVLS %f,F0" },
1010 443d6288 2012-02-19 rsc [0x0b] = { 0,0, "FCMOVUN %f,F0" },
1011 443d6288 2012-02-19 rsc [0x0d] = { Op_R1,0, "FUCOMPP" },
1014 a84cbb2a 2004-04-19 devnull static Optable optabDB[8+64] =
1016 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FMOVL %e,F0" },
1017 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FMOVL F0,%e" },
1018 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FMOVLP F0,%e" },
1019 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FMOVX %e,F0" },
1020 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FMOVXP F0,%e" },
1021 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FCMOVCC F0,F0" }, /* Mod R/M = 11xx xxxx*/
1022 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FCMOVCC F1,F0" },
1023 443d6288 2012-02-19 rsc [0x0a] = { 0,0, "FCMOVCC F2,F0" },
1024 443d6288 2012-02-19 rsc [0x0b] = { 0,0, "FCMOVCC F3,F0" },
1025 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FCMOVCC F4,F0" },
1026 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FCMOVCC F5,F0" },
1027 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FCMOVCC F6,F0" },
1028 443d6288 2012-02-19 rsc [0x0f] = { 0,0, "FCMOVCC F7,F0" },
1029 443d6288 2012-02-19 rsc [0x10] = { 0,0, "FCMOVNE F0,F0" },
1030 443d6288 2012-02-19 rsc [0x11] = { 0,0, "FCMOVNE F1,F0" },
1031 443d6288 2012-02-19 rsc [0x12] = { 0,0, "FCMOVNE F2,F0" },
1032 443d6288 2012-02-19 rsc [0x13] = { 0,0, "FCMOVNE F3,F0" },
1033 443d6288 2012-02-19 rsc [0x14] = { 0,0, "FCMOVNE F4,F0" },
1034 443d6288 2012-02-19 rsc [0x15] = { 0,0, "FCMOVNE F5,F0" },
1035 443d6288 2012-02-19 rsc [0x16] = { 0,0, "FCMOVNE F6,F0" },
1036 443d6288 2012-02-19 rsc [0x17] = { 0,0, "FCMOVNE F7,F0" },
1037 443d6288 2012-02-19 rsc [0x18] = { 0,0, "FCMOVHI F0,F0" },
1038 443d6288 2012-02-19 rsc [0x19] = { 0,0, "FCMOVHI F1,F0" },
1039 443d6288 2012-02-19 rsc [0x1a] = { 0,0, "FCMOVHI F2,F0" },
1040 443d6288 2012-02-19 rsc [0x1b] = { 0,0, "FCMOVHI F3,F0" },
1041 443d6288 2012-02-19 rsc [0x1c] = { 0,0, "FCMOVHI F4,F0" },
1042 443d6288 2012-02-19 rsc [0x1d] = { 0,0, "FCMOVHI F5,F0" },
1043 443d6288 2012-02-19 rsc [0x1e] = { 0,0, "FCMOVHI F6,F0" },
1044 443d6288 2012-02-19 rsc [0x1f] = { 0,0, "FCMOVHI F7,F0" },
1045 443d6288 2012-02-19 rsc [0x20] = { 0,0, "FCMOVNU F0,F0" },
1046 443d6288 2012-02-19 rsc [0x21] = { 0,0, "FCMOVNU F1,F0" },
1047 443d6288 2012-02-19 rsc [0x22] = { 0,0, "FCMOVNU F2,F0" },
1048 443d6288 2012-02-19 rsc [0x23] = { 0,0, "FCMOVNU F3,F0" },
1049 443d6288 2012-02-19 rsc [0x24] = { 0,0, "FCMOVNU F4,F0" },
1050 443d6288 2012-02-19 rsc [0x25] = { 0,0, "FCMOVNU F5,F0" },
1051 443d6288 2012-02-19 rsc [0x26] = { 0,0, "FCMOVNU F6,F0" },
1052 443d6288 2012-02-19 rsc [0x27] = { 0,0, "FCMOVNU F7,F0" },
1053 443d6288 2012-02-19 rsc [0x2a] = { 0,0, "FCLEX" },
1054 443d6288 2012-02-19 rsc [0x2b] = { 0,0, "FINIT" },
1055 443d6288 2012-02-19 rsc [0x30] = { 0,0, "FUCOMI F0,F0" },
1056 443d6288 2012-02-19 rsc [0x31] = { 0,0, "FUCOMI F1,F0" },
1057 443d6288 2012-02-19 rsc [0x32] = { 0,0, "FUCOMI F2,F0" },
1058 443d6288 2012-02-19 rsc [0x33] = { 0,0, "FUCOMI F3,F0" },
1059 443d6288 2012-02-19 rsc [0x34] = { 0,0, "FUCOMI F4,F0" },
1060 443d6288 2012-02-19 rsc [0x35] = { 0,0, "FUCOMI F5,F0" },
1061 443d6288 2012-02-19 rsc [0x36] = { 0,0, "FUCOMI F6,F0" },
1062 443d6288 2012-02-19 rsc [0x37] = { 0,0, "FUCOMI F7,F0" },
1063 443d6288 2012-02-19 rsc [0x38] = { 0,0, "FCOMI F0,F0" },
1064 443d6288 2012-02-19 rsc [0x39] = { 0,0, "FCOMI F1,F0" },
1065 443d6288 2012-02-19 rsc [0x3a] = { 0,0, "FCOMI F2,F0" },
1066 443d6288 2012-02-19 rsc [0x3b] = { 0,0, "FCOMI F3,F0" },
1067 443d6288 2012-02-19 rsc [0x3c] = { 0,0, "FCOMI F4,F0" },
1068 443d6288 2012-02-19 rsc [0x3d] = { 0,0, "FCOMI F5,F0" },
1069 443d6288 2012-02-19 rsc [0x3e] = { 0,0, "FCOMI F6,F0" },
1070 443d6288 2012-02-19 rsc [0x3f] = { 0,0, "FCOMI F7,F0" },
1073 a84cbb2a 2004-04-19 devnull static Optable optabDC[8+8] =
1075 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FADDD %e,F0" },
1076 443d6288 2012-02-19 rsc [0x01] = { 0,0, "FMULD %e,F0" },
1077 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FCOMD %e,F0" },
1078 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FCOMDP %e,F0" },
1079 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FSUBD %e,F0" },
1080 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FSUBRD %e,F0" },
1081 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FDIVD %e,F0" },
1082 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FDIVRD %e,F0" },
1083 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FADDD F0,%f" },
1084 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FMULD F0,%f" },
1085 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FSUBRD F0,%f" },
1086 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FSUBD F0,%f" },
1087 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FDIVRD F0,%f" },
1088 443d6288 2012-02-19 rsc [0x0f] = { 0,0, "FDIVD F0,%f" },
1091 a84cbb2a 2004-04-19 devnull static Optable optabDD[8+8] =
1093 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FMOVD %e,F0" },
1094 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FMOVD F0,%e" },
1095 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FMOVDP F0,%e" },
1096 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FRSTOR%S %e" },
1097 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FSAVE%S %e" },
1098 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FSTSW %e" },
1099 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FFREED %f" },
1100 443d6288 2012-02-19 rsc [0x0a] = { 0,0, "FMOVD %f,F0" },
1101 443d6288 2012-02-19 rsc [0x0b] = { 0,0, "FMOVDP %f,F0" },
1102 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FUCOMD %f,F0" },
1103 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FUCOMDP %f,F0" },
1106 a84cbb2a 2004-04-19 devnull static Optable optabDE[8+8] =
1108 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FADDW %e,F0" },
1109 443d6288 2012-02-19 rsc [0x01] = { 0,0, "FMULW %e,F0" },
1110 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FCOMW %e,F0" },
1111 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FCOMWP %e,F0" },
1112 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FSUBW %e,F0" },
1113 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FSUBRW %e,F0" },
1114 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FDIVW %e,F0" },
1115 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FDIVRW %e,F0" },
1116 443d6288 2012-02-19 rsc [0x08] = { 0,0, "FADDDP F0,%f" },
1117 443d6288 2012-02-19 rsc [0x09] = { 0,0, "FMULDP F0,%f" },
1118 443d6288 2012-02-19 rsc [0x0b] = { Op_R1,0, "FCOMPDP" },
1119 443d6288 2012-02-19 rsc [0x0c] = { 0,0, "FSUBRDP F0,%f" },
1120 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FSUBDP F0,%f" },
1121 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FDIVRDP F0,%f" },
1122 443d6288 2012-02-19 rsc [0x0f] = { 0,0, "FDIVDP F0,%f" },
1125 a84cbb2a 2004-04-19 devnull static Optable optabDF[8+8] =
1127 443d6288 2012-02-19 rsc [0x00] = { 0,0, "FMOVW %e,F0" },
1128 443d6288 2012-02-19 rsc [0x02] = { 0,0, "FMOVW F0,%e" },
1129 443d6288 2012-02-19 rsc [0x03] = { 0,0, "FMOVWP F0,%e" },
1130 443d6288 2012-02-19 rsc [0x04] = { 0,0, "FBLD %e" },
1131 443d6288 2012-02-19 rsc [0x05] = { 0,0, "FMOVL %e,F0" },
1132 443d6288 2012-02-19 rsc [0x06] = { 0,0, "FBSTP %e" },
1133 443d6288 2012-02-19 rsc [0x07] = { 0,0, "FMOVLP F0,%e" },
1134 443d6288 2012-02-19 rsc [0x0c] = { Op_R0,0, "FSTSW %OAX" },
1135 443d6288 2012-02-19 rsc [0x0d] = { 0,0, "FUCOMIP F0,%f" },
1136 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "FCOMIP F0,%f" },
1139 a84cbb2a 2004-04-19 devnull static Optable optabF6[8] =
1141 443d6288 2012-02-19 rsc [0x00] = { Ib,0, "TESTB %i,%e" },
1142 443d6288 2012-02-19 rsc [0x02] = { 0,0, "NOTB %e" },
1143 443d6288 2012-02-19 rsc [0x03] = { 0,0, "NEGB %e" },
1144 443d6288 2012-02-19 rsc [0x04] = { 0,0, "MULB AL,%e" },
1145 443d6288 2012-02-19 rsc [0x05] = { 0,0, "IMULB AL,%e" },
1146 443d6288 2012-02-19 rsc [0x06] = { 0,0, "DIVB AL,%e" },
1147 443d6288 2012-02-19 rsc [0x07] = { 0,0, "IDIVB AL,%e" },
1150 a84cbb2a 2004-04-19 devnull static Optable optabF7[8] =
1152 443d6288 2012-02-19 rsc [0x00] = { Iwd,0, "TEST%S %i,%e" },
1153 443d6288 2012-02-19 rsc [0x02] = { 0,0, "NOT%S %e" },
1154 443d6288 2012-02-19 rsc [0x03] = { 0,0, "NEG%S %e" },
1155 443d6288 2012-02-19 rsc [0x04] = { 0,0, "MUL%S %OAX,%e" },
1156 443d6288 2012-02-19 rsc [0x05] = { 0,0, "IMUL%S %OAX,%e" },
1157 443d6288 2012-02-19 rsc [0x06] = { 0,0, "DIV%S %OAX,%e" },
1158 443d6288 2012-02-19 rsc [0x07] = { 0,0, "IDIV%S %OAX,%e" },
1161 a84cbb2a 2004-04-19 devnull static Optable optabFE[8] =
1163 443d6288 2012-02-19 rsc [0x00] = { 0,0, "INCB %e" },
1164 443d6288 2012-02-19 rsc [0x01] = { 0,0, "DECB %e" },
1167 a84cbb2a 2004-04-19 devnull static Optable optabFF[8] =
1169 443d6288 2012-02-19 rsc [0x00] = { 0,0, "INC%S %e" },
1170 443d6288 2012-02-19 rsc [0x01] = { 0,0, "DEC%S %e" },
1171 443d6288 2012-02-19 rsc [0x02] = { JUMP,0, "CALL* %e" },
1172 443d6288 2012-02-19 rsc [0x03] = { JUMP,0, "CALLF* %e" },
1173 443d6288 2012-02-19 rsc [0x04] = { JUMP,0, "JMP* %e" },
1174 443d6288 2012-02-19 rsc [0x05] = { JUMP,0, "JMPF* %e" },
1175 443d6288 2012-02-19 rsc [0x06] = { 0,0, "PUSHL %e" },
1178 443d6288 2012-02-19 rsc static Optable optable[256+2] =
1180 443d6288 2012-02-19 rsc [0x00] = { RMB,0, "ADDB %r,%e" },
1181 443d6288 2012-02-19 rsc [0x01] = { RM,0, "ADD%S %r,%e" },
1182 443d6288 2012-02-19 rsc [0x02] = { RMB,0, "ADDB %e,%r" },
1183 443d6288 2012-02-19 rsc [0x03] = { RM,0, "ADD%S %e,%r" },
1184 443d6288 2012-02-19 rsc [0x04] = { Ib,0, "ADDB %i,AL" },
1185 443d6288 2012-02-19 rsc [0x05] = { Iwd,0, "ADD%S %i,%OAX" },
1186 443d6288 2012-02-19 rsc [0x06] = { 0,0, "PUSHL ES" },
1187 443d6288 2012-02-19 rsc [0x07] = { 0,0, "POPL ES" },
1188 443d6288 2012-02-19 rsc [0x08] = { RMB,0, "ORB %r,%e" },
1189 443d6288 2012-02-19 rsc [0x09] = { RM,0, "OR%S %r,%e" },
1190 443d6288 2012-02-19 rsc [0x0a] = { RMB,0, "ORB %e,%r" },
1191 443d6288 2012-02-19 rsc [0x0b] = { RM,0, "OR%S %e,%r" },
1192 443d6288 2012-02-19 rsc [0x0c] = { Ib,0, "ORB %i,AL" },
1193 443d6288 2012-02-19 rsc [0x0d] = { Iwd,0, "OR%S %i,%OAX" },
1194 443d6288 2012-02-19 rsc [0x0e] = { 0,0, "PUSHL CS" },
1195 443d6288 2012-02-19 rsc [0x0f] = { AUXMM,0, optab0F },
1196 443d6288 2012-02-19 rsc [0x10] = { RMB,0, "ADCB %r,%e" },
1197 443d6288 2012-02-19 rsc [0x11] = { RM,0, "ADC%S %r,%e" },
1198 443d6288 2012-02-19 rsc [0x12] = { RMB,0, "ADCB %e,%r" },
1199 443d6288 2012-02-19 rsc [0x13] = { RM,0, "ADC%S %e,%r" },
1200 443d6288 2012-02-19 rsc [0x14] = { Ib,0, "ADCB %i,AL" },
1201 443d6288 2012-02-19 rsc [0x15] = { Iwd,0, "ADC%S %i,%OAX" },
1202 443d6288 2012-02-19 rsc [0x16] = { 0,0, "PUSHL SS" },
1203 443d6288 2012-02-19 rsc [0x17] = { 0,0, "POPL SS" },
1204 443d6288 2012-02-19 rsc [0x18] = { RMB,0, "SBBB %r,%e" },
1205 443d6288 2012-02-19 rsc [0x19] = { RM,0, "SBB%S %r,%e" },
1206 443d6288 2012-02-19 rsc [0x1a] = { RMB,0, "SBBB %e,%r" },
1207 443d6288 2012-02-19 rsc [0x1b] = { RM,0, "SBB%S %e,%r" },
1208 443d6288 2012-02-19 rsc [0x1c] = { Ib,0, "SBBB %i,AL" },
1209 443d6288 2012-02-19 rsc [0x1d] = { Iwd,0, "SBB%S %i,%OAX" },
1210 443d6288 2012-02-19 rsc [0x1e] = { 0,0, "PUSHL DS" },
1211 443d6288 2012-02-19 rsc [0x1f] = { 0,0, "POPL DS" },
1212 443d6288 2012-02-19 rsc [0x20] = { RMB,0, "ANDB %r,%e" },
1213 443d6288 2012-02-19 rsc [0x21] = { RM,0, "AND%S %r,%e" },
1214 443d6288 2012-02-19 rsc [0x22] = { RMB,0, "ANDB %e,%r" },
1215 443d6288 2012-02-19 rsc [0x23] = { RM,0, "AND%S %e,%r" },
1216 443d6288 2012-02-19 rsc [0x24] = { Ib,0, "ANDB %i,AL" },
1217 443d6288 2012-02-19 rsc [0x25] = { Iwd,0, "AND%S %i,%OAX" },
1218 443d6288 2012-02-19 rsc [0x26] = { SEG,0, "ES:" },
1219 443d6288 2012-02-19 rsc [0x27] = { 0,0, "DAA" },
1220 443d6288 2012-02-19 rsc [0x28] = { RMB,0, "SUBB %r,%e" },
1221 443d6288 2012-02-19 rsc [0x29] = { RM,0, "SUB%S %r,%e" },
1222 443d6288 2012-02-19 rsc [0x2a] = { RMB,0, "SUBB %e,%r" },
1223 443d6288 2012-02-19 rsc [0x2b] = { RM,0, "SUB%S %e,%r" },
1224 443d6288 2012-02-19 rsc [0x2c] = { Ib,0, "SUBB %i,AL" },
1225 443d6288 2012-02-19 rsc [0x2d] = { Iwd,0, "SUB%S %i,%OAX" },
1226 443d6288 2012-02-19 rsc [0x2e] = { SEG,0, "CS:" },
1227 443d6288 2012-02-19 rsc [0x2f] = { 0,0, "DAS" },
1228 443d6288 2012-02-19 rsc [0x30] = { RMB,0, "XORB %r,%e" },
1229 443d6288 2012-02-19 rsc [0x31] = { RM,0, "XOR%S %r,%e" },
1230 443d6288 2012-02-19 rsc [0x32] = { RMB,0, "XORB %e,%r" },
1231 443d6288 2012-02-19 rsc [0x33] = { RM,0, "XOR%S %e,%r" },
1232 443d6288 2012-02-19 rsc [0x34] = { Ib,0, "XORB %i,AL" },
1233 443d6288 2012-02-19 rsc [0x35] = { Iwd,0, "XOR%S %i,%OAX" },
1234 443d6288 2012-02-19 rsc [0x36] = { SEG,0, "SS:" },
1235 443d6288 2012-02-19 rsc [0x37] = { 0,0, "AAA" },
1236 443d6288 2012-02-19 rsc [0x38] = { RMB,0, "CMPB %r,%e" },
1237 443d6288 2012-02-19 rsc [0x39] = { RM,0, "CMP%S %r,%e" },
1238 443d6288 2012-02-19 rsc [0x3a] = { RMB,0, "CMPB %e,%r" },
1239 443d6288 2012-02-19 rsc [0x3b] = { RM,0, "CMP%S %e,%r" },
1240 443d6288 2012-02-19 rsc [0x3c] = { Ib,0, "CMPB %i,AL" },
1241 443d6288 2012-02-19 rsc [0x3d] = { Iwd,0, "CMP%S %i,%OAX" },
1242 443d6288 2012-02-19 rsc [0x3e] = { SEG,0, "DS:" },
1243 443d6288 2012-02-19 rsc [0x3f] = { 0,0, "AAS" },
1244 443d6288 2012-02-19 rsc [0x40] = { 0,0, "INC%S %OAX" },
1245 443d6288 2012-02-19 rsc [0x41] = { 0,0, "INC%S %OCX" },
1246 443d6288 2012-02-19 rsc [0x42] = { 0,0, "INC%S %ODX" },
1247 443d6288 2012-02-19 rsc [0x43] = { 0,0, "INC%S %OBX" },
1248 443d6288 2012-02-19 rsc [0x44] = { 0,0, "INC%S %OSP" },
1249 443d6288 2012-02-19 rsc [0x45] = { 0,0, "INC%S %OBP" },
1250 443d6288 2012-02-19 rsc [0x46] = { 0,0, "INC%S %OSI" },
1251 443d6288 2012-02-19 rsc [0x47] = { 0,0, "INC%S %ODI" },
1252 443d6288 2012-02-19 rsc [0x48] = { 0,0, "DEC%S %OAX" },
1253 443d6288 2012-02-19 rsc [0x49] = { 0,0, "DEC%S %OCX" },
1254 443d6288 2012-02-19 rsc [0x4a] = { 0,0, "DEC%S %ODX" },
1255 443d6288 2012-02-19 rsc [0x4b] = { 0,0, "DEC%S %OBX" },
1256 443d6288 2012-02-19 rsc [0x4c] = { 0,0, "DEC%S %OSP" },
1257 443d6288 2012-02-19 rsc [0x4d] = { 0,0, "DEC%S %OBP" },
1258 443d6288 2012-02-19 rsc [0x4e] = { 0,0, "DEC%S %OSI" },
1259 443d6288 2012-02-19 rsc [0x4f] = { 0,0, "DEC%S %ODI" },
1260 443d6288 2012-02-19 rsc [0x50] = { 0,0, "PUSH%S %OAX" },
1261 443d6288 2012-02-19 rsc [0x51] = { 0,0, "PUSH%S %OCX" },
1262 443d6288 2012-02-19 rsc [0x52] = { 0,0, "PUSH%S %ODX" },
1263 443d6288 2012-02-19 rsc [0x53] = { 0,0, "PUSH%S %OBX" },
1264 443d6288 2012-02-19 rsc [0x54] = { 0,0, "PUSH%S %OSP" },
1265 443d6288 2012-02-19 rsc [0x55] = { 0,0, "PUSH%S %OBP" },
1266 443d6288 2012-02-19 rsc [0x56] = { 0,0, "PUSH%S %OSI" },
1267 443d6288 2012-02-19 rsc [0x57] = { 0,0, "PUSH%S %ODI" },
1268 443d6288 2012-02-19 rsc [0x58] = { 0,0, "POP%S %OAX" },
1269 443d6288 2012-02-19 rsc [0x59] = { 0,0, "POP%S %OCX" },
1270 443d6288 2012-02-19 rsc [0x5a] = { 0,0, "POP%S %ODX" },
1271 443d6288 2012-02-19 rsc [0x5b] = { 0,0, "POP%S %OBX" },
1272 443d6288 2012-02-19 rsc [0x5c] = { 0,0, "POP%S %OSP" },
1273 443d6288 2012-02-19 rsc [0x5d] = { 0,0, "POP%S %OBP" },
1274 443d6288 2012-02-19 rsc [0x5e] = { 0,0, "POP%S %OSI" },
1275 443d6288 2012-02-19 rsc [0x5f] = { 0,0, "POP%S %ODI" },
1276 443d6288 2012-02-19 rsc [0x60] = { 0,0, "PUSHA%S" },
1277 443d6288 2012-02-19 rsc [0x61] = { 0,0, "POPA%S" },
1278 443d6288 2012-02-19 rsc [0x62] = { RMM,0, "BOUND %e,%r" },
1279 443d6288 2012-02-19 rsc [0x63] = { RM,0, "ARPL %r,%e" },
1280 443d6288 2012-02-19 rsc [0x64] = { SEG,0, "FS:" },
1281 443d6288 2012-02-19 rsc [0x65] = { SEG,0, "GS:" },
1282 443d6288 2012-02-19 rsc [0x66] = { OPOVER,0, "" },
1283 443d6288 2012-02-19 rsc [0x67] = { ADDOVER,0, "" },
1284 443d6288 2012-02-19 rsc [0x68] = { Iwd,0, "PUSH%S %i" },
1285 443d6288 2012-02-19 rsc [0x69] = { RM,Iwd, "IMUL%S %e,%i,%r" },
1286 443d6288 2012-02-19 rsc [0x6a] = { Ib,0, "PUSH%S %i" },
1287 443d6288 2012-02-19 rsc [0x6b] = { RM,Ibs, "IMUL%S %e,%i,%r" },
1288 443d6288 2012-02-19 rsc [0x6c] = { 0,0, "INSB DX,(%ODI)" },
1289 443d6288 2012-02-19 rsc [0x6d] = { 0,0, "INS%S DX,(%ODI)" },
1290 443d6288 2012-02-19 rsc [0x6e] = { 0,0, "OUTSB (%ASI),DX" },
1291 443d6288 2012-02-19 rsc [0x6f] = { 0,0, "OUTS%S (%ASI),DX" },
1292 443d6288 2012-02-19 rsc [0x70] = { Jbs,0, "JOS %p" },
1293 443d6288 2012-02-19 rsc [0x71] = { Jbs,0, "JOC %p" },
1294 443d6288 2012-02-19 rsc [0x72] = { Jbs,0, "JCS %p" },
1295 443d6288 2012-02-19 rsc [0x73] = { Jbs,0, "JCC %p" },
1296 443d6288 2012-02-19 rsc [0x74] = { Jbs,0, "JEQ %p" },
1297 443d6288 2012-02-19 rsc [0x75] = { Jbs,0, "JNE %p" },
1298 443d6288 2012-02-19 rsc [0x76] = { Jbs,0, "JLS %p" },
1299 443d6288 2012-02-19 rsc [0x77] = { Jbs,0, "JHI %p" },
1300 443d6288 2012-02-19 rsc [0x78] = { Jbs,0, "JMI %p" },
1301 443d6288 2012-02-19 rsc [0x79] = { Jbs,0, "JPL %p" },
1302 443d6288 2012-02-19 rsc [0x7a] = { Jbs,0, "JPS %p" },
1303 443d6288 2012-02-19 rsc [0x7b] = { Jbs,0, "JPC %p" },
1304 443d6288 2012-02-19 rsc [0x7c] = { Jbs,0, "JLT %p" },
1305 443d6288 2012-02-19 rsc [0x7d] = { Jbs,0, "JGE %p" },
1306 443d6288 2012-02-19 rsc [0x7e] = { Jbs,0, "JLE %p" },
1307 443d6288 2012-02-19 rsc [0x7f] = { Jbs,0, "JGT %p" },
1308 443d6288 2012-02-19 rsc [0x80] = { RMOPB,0, optab80 },
1309 443d6288 2012-02-19 rsc [0x81] = { RMOP,0, optab81 },
1310 443d6288 2012-02-19 rsc [0x83] = { RMOP,0, optab83 },
1311 443d6288 2012-02-19 rsc [0x84] = { RMB,0, "TESTB %r,%e" },
1312 443d6288 2012-02-19 rsc [0x85] = { RM,0, "TEST%S %r,%e" },
1313 443d6288 2012-02-19 rsc [0x86] = { RMB,0, "XCHGB %r,%e" },
1314 443d6288 2012-02-19 rsc [0x87] = { RM,0, "XCHG%S %r,%e" },
1315 443d6288 2012-02-19 rsc [0x88] = { RMB,0, "MOVB %r,%e" },
1316 443d6288 2012-02-19 rsc [0x89] = { RM,0, "MOV%S %r,%e" },
1317 443d6288 2012-02-19 rsc [0x8a] = { RMB,0, "MOVB %e,%r" },
1318 443d6288 2012-02-19 rsc [0x8b] = { RM,0, "MOV%S %e,%r" },
1319 443d6288 2012-02-19 rsc [0x8c] = { RM,0, "MOVW %g,%e" },
1320 443d6288 2012-02-19 rsc [0x8d] = { RM,0, "LEA%S %e,%r" },
1321 443d6288 2012-02-19 rsc [0x8e] = { RM,0, "MOVW %e,%g" },
1322 443d6288 2012-02-19 rsc [0x8f] = { RM,0, "POP%S %e" },
1323 443d6288 2012-02-19 rsc [0x90] = { 0,0, "NOP" },
1324 443d6288 2012-02-19 rsc [0x91] = { 0,0, "XCHG %OCX,%OAX" },
1325 443d6288 2012-02-19 rsc [0x92] = { 0,0, "XCHG %ODX,%OAX" },
1326 443d6288 2012-02-19 rsc [0x93] = { 0,0, "XCHG %OBX,%OAX" },
1327 443d6288 2012-02-19 rsc [0x94] = { 0,0, "XCHG %OSP,%OAX" },
1328 443d6288 2012-02-19 rsc [0x95] = { 0,0, "XCHG %OBP,%OAX" },
1329 443d6288 2012-02-19 rsc [0x96] = { 0,0, "XCHG %OSI,%OAX" },
1330 443d6288 2012-02-19 rsc [0x97] = { 0,0, "XCHG %ODI,%OAX" },
1331 443d6288 2012-02-19 rsc [0x98] = { 0,0, "%W" }, /* miserable CBW or CWDE */
1332 443d6288 2012-02-19 rsc [0x99] = { 0,0, "%w" }, /* idiotic CWD or CDQ */
1333 443d6288 2012-02-19 rsc [0x9a] = { PTR,0, "CALL%S %d" },
1334 443d6288 2012-02-19 rsc [0x9b] = { 0,0, "WAIT" },
1335 443d6288 2012-02-19 rsc [0x9c] = { 0,0, "PUSHF" },
1336 443d6288 2012-02-19 rsc [0x9d] = { 0,0, "POPF" },
1337 443d6288 2012-02-19 rsc [0x9e] = { 0,0, "SAHF" },
1338 443d6288 2012-02-19 rsc [0x9f] = { 0,0, "LAHF" },
1339 443d6288 2012-02-19 rsc [0xa0] = { Awd,0, "MOVB %i,AL" },
1340 443d6288 2012-02-19 rsc [0xa1] = { Awd,0, "MOV%S %i,%OAX" },
1341 443d6288 2012-02-19 rsc [0xa2] = { Awd,0, "MOVB AL,%i" },
1342 443d6288 2012-02-19 rsc [0xa3] = { Awd,0, "MOV%S %OAX,%i" },
1343 443d6288 2012-02-19 rsc [0xa4] = { 0,0, "MOVSB (%ASI),(%ADI)" },
1344 443d6288 2012-02-19 rsc [0xa5] = { 0,0, "MOVS%S (%ASI),(%ADI)" },
1345 443d6288 2012-02-19 rsc [0xa6] = { 0,0, "CMPSB (%ASI),(%ADI)" },
1346 443d6288 2012-02-19 rsc [0xa7] = { 0,0, "CMPS%S (%ASI),(%ADI)" },
1347 443d6288 2012-02-19 rsc [0xa8] = { Ib,0, "TESTB %i,AL" },
1348 443d6288 2012-02-19 rsc [0xa9] = { Iwd,0, "TEST%S %i,%OAX" },
1349 443d6288 2012-02-19 rsc [0xaa] = { 0,0, "STOSB AL,(%ADI)" },
1350 443d6288 2012-02-19 rsc [0xab] = { 0,0, "STOS%S %OAX,(%ADI)" },
1351 443d6288 2012-02-19 rsc [0xac] = { 0,0, "LODSB (%ASI),AL" },
1352 443d6288 2012-02-19 rsc [0xad] = { 0,0, "LODS%S (%ASI),%OAX" },
1353 443d6288 2012-02-19 rsc [0xae] = { 0,0, "SCASB (%ADI),AL" },
1354 443d6288 2012-02-19 rsc [0xaf] = { 0,0, "SCAS%S (%ADI),%OAX" },
1355 443d6288 2012-02-19 rsc [0xb0] = { Ib,0, "MOVB %i,AL" },
1356 443d6288 2012-02-19 rsc [0xb1] = { Ib,0, "MOVB %i,CL" },
1357 443d6288 2012-02-19 rsc [0xb2] = { Ib,0, "MOVB %i,DL" },
1358 443d6288 2012-02-19 rsc [0xb3] = { Ib,0, "MOVB %i,BL" },
1359 443d6288 2012-02-19 rsc [0xb4] = { Ib,0, "MOVB %i,AH" },
1360 443d6288 2012-02-19 rsc [0xb5] = { Ib,0, "MOVB %i,CH" },
1361 443d6288 2012-02-19 rsc [0xb6] = { Ib,0, "MOVB %i,DH" },
1362 443d6288 2012-02-19 rsc [0xb7] = { Ib,0, "MOVB %i,BH" },
1363 443d6288 2012-02-19 rsc [0xb8] = { Iwdq,0, "MOV%S %i,%OAX" },
1364 443d6288 2012-02-19 rsc [0xb9] = { Iwdq,0, "MOV%S %i,%OCX" },
1365 443d6288 2012-02-19 rsc [0xba] = { Iwdq,0, "MOV%S %i,%ODX" },
1366 443d6288 2012-02-19 rsc [0xbb] = { Iwdq,0, "MOV%S %i,%OBX" },
1367 443d6288 2012-02-19 rsc [0xbc] = { Iwdq,0, "MOV%S %i,%OSP" },
1368 443d6288 2012-02-19 rsc [0xbd] = { Iwdq,0, "MOV%S %i,%OBP" },
1369 443d6288 2012-02-19 rsc [0xbe] = { Iwdq,0, "MOV%S %i,%OSI" },
1370 443d6288 2012-02-19 rsc [0xbf] = { Iwdq,0, "MOV%S %i,%ODI" },
1371 443d6288 2012-02-19 rsc [0xc0] = { RMOPB,0, optabC0 },
1372 443d6288 2012-02-19 rsc [0xc1] = { RMOP,0, optabC1 },
1373 443d6288 2012-02-19 rsc [0xc2] = { Iw,0, "RET %i" },
1374 443d6288 2012-02-19 rsc [0xc3] = { RET,0, "RET" },
1375 443d6288 2012-02-19 rsc [0xc4] = { RM,0, "LES %e,%r" },
1376 443d6288 2012-02-19 rsc [0xc5] = { RM,0, "LDS %e,%r" },
1377 443d6288 2012-02-19 rsc [0xc6] = { RMB,Ib, "MOVB %i,%e" },
1378 443d6288 2012-02-19 rsc [0xc7] = { RM,Iwd, "MOV%S %i,%e" },
1379 443d6288 2012-02-19 rsc [0xc8] = { Iw2,Ib, "ENTER %i,%I" }, /* loony ENTER */
1380 443d6288 2012-02-19 rsc [0xc9] = { RET,0, "LEAVE" }, /* bizarre LEAVE */
1381 443d6288 2012-02-19 rsc [0xca] = { Iw,0, "RETF %i" },
1382 443d6288 2012-02-19 rsc [0xcb] = { RET,0, "RETF" },
1383 443d6288 2012-02-19 rsc [0xcc] = { 0,0, "INT 3" },
1384 443d6288 2012-02-19 rsc [0xcd] = { Ib,0, "INTB %i" },
1385 443d6288 2012-02-19 rsc [0xce] = { 0,0, "INTO" },
1386 443d6288 2012-02-19 rsc [0xcf] = { 0,0, "IRET" },
1387 443d6288 2012-02-19 rsc [0xd0] = { RMOPB,0, optabD0 },
1388 443d6288 2012-02-19 rsc [0xd1] = { RMOP,0, optabD1 },
1389 443d6288 2012-02-19 rsc [0xd2] = { RMOPB,0, optabD2 },
1390 443d6288 2012-02-19 rsc [0xd3] = { RMOP,0, optabD3 },
1391 443d6288 2012-02-19 rsc [0xd4] = { OA,0, "AAM" },
1392 443d6288 2012-02-19 rsc [0xd5] = { OA,0, "AAD" },
1393 443d6288 2012-02-19 rsc [0xd7] = { 0,0, "XLAT" },
1394 443d6288 2012-02-19 rsc [0xd8] = { FRMOP,0, optabD8 },
1395 443d6288 2012-02-19 rsc [0xd9] = { FRMEX,0, optabD9 },
1396 443d6288 2012-02-19 rsc [0xda] = { FRMOP,0, optabDA },
1397 443d6288 2012-02-19 rsc [0xdb] = { FRMEX,0, optabDB },
1398 443d6288 2012-02-19 rsc [0xdc] = { FRMOP,0, optabDC },
1399 443d6288 2012-02-19 rsc [0xdd] = { FRMOP,0, optabDD },
1400 443d6288 2012-02-19 rsc [0xde] = { FRMOP,0, optabDE },
1401 443d6288 2012-02-19 rsc [0xdf] = { FRMOP,0, optabDF },
1402 443d6288 2012-02-19 rsc [0xe0] = { Jbs,0, "LOOPNE %p" },
1403 443d6288 2012-02-19 rsc [0xe1] = { Jbs,0, "LOOPE %p" },
1404 443d6288 2012-02-19 rsc [0xe2] = { Jbs,0, "LOOP %p" },
1405 443d6288 2012-02-19 rsc [0xe3] = { Jbs,0, "JCXZ %p" },
1406 443d6288 2012-02-19 rsc [0xe4] = { Ib,0, "INB %i,AL" },
1407 443d6288 2012-02-19 rsc [0xe5] = { Ib,0, "IN%S %i,%OAX" },
1408 443d6288 2012-02-19 rsc [0xe6] = { Ib,0, "OUTB AL,%i" },
1409 443d6288 2012-02-19 rsc [0xe7] = { Ib,0, "OUT%S %OAX,%i" },
1410 443d6288 2012-02-19 rsc [0xe8] = { Iwds,0, "CALL %p" },
1411 443d6288 2012-02-19 rsc [0xe9] = { Iwds,0, "JMP %p" },
1412 443d6288 2012-02-19 rsc [0xea] = { PTR,0, "JMP %d" },
1413 443d6288 2012-02-19 rsc [0xeb] = { Jbs,0, "JMP %p" },
1414 443d6288 2012-02-19 rsc [0xec] = { 0,0, "INB DX,AL" },
1415 443d6288 2012-02-19 rsc [0xed] = { 0,0, "IN%S DX,%OAX" },
1416 443d6288 2012-02-19 rsc [0xee] = { 0,0, "OUTB AL,DX" },
1417 443d6288 2012-02-19 rsc [0xef] = { 0,0, "OUT%S %OAX,DX" },
1418 443d6288 2012-02-19 rsc [0xf0] = { PRE,0, "LOCK" },
1419 443d6288 2012-02-19 rsc [0xf2] = { OPRE,0, "REPNE" },
1420 443d6288 2012-02-19 rsc [0xf3] = { OPRE,0, "REP" },
1421 443d6288 2012-02-19 rsc [0xf4] = { 0,0, "HLT" },
1422 443d6288 2012-02-19 rsc [0xf5] = { 0,0, "CMC" },
1423 443d6288 2012-02-19 rsc [0xf6] = { RMOPB,0, optabF6 },
1424 443d6288 2012-02-19 rsc [0xf7] = { RMOP,0, optabF7 },
1425 443d6288 2012-02-19 rsc [0xf8] = { 0,0, "CLC" },
1426 443d6288 2012-02-19 rsc [0xf9] = { 0,0, "STC" },
1427 443d6288 2012-02-19 rsc [0xfa] = { 0,0, "CLI" },
1428 443d6288 2012-02-19 rsc [0xfb] = { 0,0, "STI" },
1429 443d6288 2012-02-19 rsc [0xfc] = { 0,0, "CLD" },
1430 443d6288 2012-02-19 rsc [0xfd] = { 0,0, "STD" },
1431 443d6288 2012-02-19 rsc [0xfe] = { RMOPB,0, optabFE },
1432 443d6288 2012-02-19 rsc [0xff] = { RMOP,0, optabFF },
1433 443d6288 2012-02-19 rsc [0x100] = { RM,0, "MOVLQSX %e,%r" },
1434 443d6288 2012-02-19 rsc [0x101] = { RM,0, "MOVLQZX %e,%r" },
1438 a84cbb2a 2004-04-19 devnull * get a byte of the instruction
1440 a84cbb2a 2004-04-19 devnull static int
1441 443d6288 2012-02-19 rsc igetc(Map *map, Instr *ip, uchar *c)
1443 a84cbb2a 2004-04-19 devnull if(ip->n+1 > sizeof(ip->mem)){
1444 a84cbb2a 2004-04-19 devnull werrstr("instruction too long");
1445 a84cbb2a 2004-04-19 devnull return -1;
1447 a84cbb2a 2004-04-19 devnull if (get1(map, ip->addr+ip->n, c, 1) < 0) {
1448 a84cbb2a 2004-04-19 devnull werrstr("can't read instruction: %r");
1449 a84cbb2a 2004-04-19 devnull return -1;
1451 a84cbb2a 2004-04-19 devnull ip->mem[ip->n++] = *c;
1452 a84cbb2a 2004-04-19 devnull return 1;
1456 a84cbb2a 2004-04-19 devnull * get two bytes of the instruction
1458 a84cbb2a 2004-04-19 devnull static int
1459 a84cbb2a 2004-04-19 devnull igets(Map *map, Instr *ip, ushort *sp)
1462 a84cbb2a 2004-04-19 devnull ushort s;
1464 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1465 a84cbb2a 2004-04-19 devnull return -1;
1467 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1468 a84cbb2a 2004-04-19 devnull return -1;
1469 a84cbb2a 2004-04-19 devnull s |= (c<<8);
1470 a84cbb2a 2004-04-19 devnull *sp = s;
1471 a84cbb2a 2004-04-19 devnull return 1;
1475 a84cbb2a 2004-04-19 devnull * get 4 bytes of the instruction
1477 a84cbb2a 2004-04-19 devnull static int
1478 443d6288 2012-02-19 rsc igetl(Map *map, Instr *ip, uint32 *lp)
1480 a84cbb2a 2004-04-19 devnull ushort s;
1483 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s) < 0)
1484 a84cbb2a 2004-04-19 devnull return -1;
1486 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s) < 0)
1487 a84cbb2a 2004-04-19 devnull return -1;
1488 a84cbb2a 2004-04-19 devnull l |= (s<<16);
1489 a84cbb2a 2004-04-19 devnull *lp = l;
1490 a84cbb2a 2004-04-19 devnull return 1;
1494 443d6288 2012-02-19 rsc * get 8 bytes of the instruction
1496 a84cbb2a 2004-04-19 devnull static int
1497 443d6288 2012-02-19 rsc igetq(Map *map, Instr *ip, vlong *qp)
1502 443d6288 2012-02-19 rsc if (igetl(map, ip, &l) < 0)
1505 443d6288 2012-02-19 rsc if (igetl(map, ip, &l) < 0)
1507 443d6288 2012-02-19 rsc q |= ((uvlong)l<<32);
1514 443d6288 2012-02-19 rsc getdisp(Map *map, Instr *ip, int mod, int rm, int code, int pcrel)
1516 a84cbb2a 2004-04-19 devnull uchar c;
1517 a84cbb2a 2004-04-19 devnull ushort s;
1519 a84cbb2a 2004-04-19 devnull if (mod > 2)
1520 a84cbb2a 2004-04-19 devnull return 1;
1521 a84cbb2a 2004-04-19 devnull if (mod == 1) {
1522 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1523 a84cbb2a 2004-04-19 devnull return -1;
1524 a84cbb2a 2004-04-19 devnull if (c&0x80)
1525 a84cbb2a 2004-04-19 devnull ip->disp = c|0xffffff00;
1527 a84cbb2a 2004-04-19 devnull ip->disp = c&0xff;
1528 a84cbb2a 2004-04-19 devnull } else if (mod == 2 || rm == code) {
1529 a84cbb2a 2004-04-19 devnull if (ip->asize == 'E') {
1530 a84cbb2a 2004-04-19 devnull if (igetl(map, ip, &ip->disp) < 0)
1531 a84cbb2a 2004-04-19 devnull return -1;
1532 443d6288 2012-02-19 rsc if (mod == 0)
1533 443d6288 2012-02-19 rsc ip->rip = pcrel;
1534 a84cbb2a 2004-04-19 devnull } else {
1535 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s) < 0)
1536 a84cbb2a 2004-04-19 devnull return -1;
1537 a84cbb2a 2004-04-19 devnull if (s&0x8000)
1538 a84cbb2a 2004-04-19 devnull ip->disp = s|0xffff0000;
1540 a84cbb2a 2004-04-19 devnull ip->disp = s;
1542 a84cbb2a 2004-04-19 devnull if (mod == 0)
1543 a84cbb2a 2004-04-19 devnull ip->base = -1;
1545 a84cbb2a 2004-04-19 devnull return 1;
1548 a84cbb2a 2004-04-19 devnull static int
1549 a84cbb2a 2004-04-19 devnull modrm(Map *map, Instr *ip, uchar c)
1551 a84cbb2a 2004-04-19 devnull uchar rm, mod;
1553 a84cbb2a 2004-04-19 devnull mod = (c>>6)&3;
1554 a84cbb2a 2004-04-19 devnull rm = c&7;
1555 a84cbb2a 2004-04-19 devnull ip->mod = mod;
1556 a84cbb2a 2004-04-19 devnull ip->base = rm;
1557 a84cbb2a 2004-04-19 devnull ip->reg = (c>>3)&7;
1558 443d6288 2012-02-19 rsc ip->rip = 0;
1559 a84cbb2a 2004-04-19 devnull if (mod == 3) /* register */
1560 a84cbb2a 2004-04-19 devnull return 1;
1561 a84cbb2a 2004-04-19 devnull if (ip->asize == 0) { /* 16-bit mode */
1562 443d6288 2012-02-19 rsc switch(rm) {
1563 a84cbb2a 2004-04-19 devnull case 0:
1564 a84cbb2a 2004-04-19 devnull ip->base = BX; ip->index = SI;
1566 a84cbb2a 2004-04-19 devnull case 1:
1567 a84cbb2a 2004-04-19 devnull ip->base = BX; ip->index = DI;
1569 a84cbb2a 2004-04-19 devnull case 2:
1570 a84cbb2a 2004-04-19 devnull ip->base = BP; ip->index = SI;
1572 a84cbb2a 2004-04-19 devnull case 3:
1573 a84cbb2a 2004-04-19 devnull ip->base = BP; ip->index = DI;
1575 a84cbb2a 2004-04-19 devnull case 4:
1576 a84cbb2a 2004-04-19 devnull ip->base = SI;
1578 a84cbb2a 2004-04-19 devnull case 5:
1579 a84cbb2a 2004-04-19 devnull ip->base = DI;
1581 a84cbb2a 2004-04-19 devnull case 6:
1582 a84cbb2a 2004-04-19 devnull ip->base = BP;
1584 a84cbb2a 2004-04-19 devnull case 7:
1585 a84cbb2a 2004-04-19 devnull ip->base = BX;
1587 a84cbb2a 2004-04-19 devnull default:
1590 443d6288 2012-02-19 rsc return getdisp(map, ip, mod, rm, 6, 0);
1592 a84cbb2a 2004-04-19 devnull if (rm == 4) { /* scummy sib byte */
1593 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1594 a84cbb2a 2004-04-19 devnull return -1;
1595 a84cbb2a 2004-04-19 devnull ip->ss = (c>>6)&0x03;
1596 a84cbb2a 2004-04-19 devnull ip->index = (c>>3)&0x07;
1597 a84cbb2a 2004-04-19 devnull if (ip->index == 4)
1598 a84cbb2a 2004-04-19 devnull ip->index = -1;
1599 a84cbb2a 2004-04-19 devnull ip->base = c&0x07;
1600 443d6288 2012-02-19 rsc return getdisp(map, ip, mod, ip->base, 5, 0);
1602 443d6288 2012-02-19 rsc return getdisp(map, ip, mod, rm, 5, ip->amd64);
1605 a84cbb2a 2004-04-19 devnull static Optable *
1606 443d6288 2012-02-19 rsc mkinstr(Map *map, Instr *ip, uvlong pc)
1608 443d6288 2012-02-19 rsc int i, n, norex;
1609 a84cbb2a 2004-04-19 devnull uchar c;
1610 a84cbb2a 2004-04-19 devnull ushort s;
1611 a84cbb2a 2004-04-19 devnull Optable *op, *obase;
1612 a84cbb2a 2004-04-19 devnull char buf[128];
1614 a84cbb2a 2004-04-19 devnull memset(ip, 0, sizeof(*ip));
1616 a84cbb2a 2004-04-19 devnull ip->base = -1;
1617 a84cbb2a 2004-04-19 devnull ip->index = -1;
1618 443d6288 2012-02-19 rsc // if(asstype == AI8086)
1619 443d6288 2012-02-19 rsc // ip->osize = 'W';
1621 a84cbb2a 2004-04-19 devnull ip->osize = 'L';
1622 a84cbb2a 2004-04-19 devnull ip->asize = 'E';
1623 443d6288 2012-02-19 rsc ip->amd64 = (machcpu == &machamd64);
1626 a84cbb2a 2004-04-19 devnull ip->addr = pc;
1627 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1628 a84cbb2a 2004-04-19 devnull return 0;
1629 a84cbb2a 2004-04-19 devnull obase = optable;
1631 443d6288 2012-02-19 rsc if(ip->amd64 && !norex){
1632 443d6288 2012-02-19 rsc if(c >= 0x40 && c <= 0x4f) {
1633 443d6288 2012-02-19 rsc ip->rex = c;
1634 443d6288 2012-02-19 rsc if(igetc(map, ip, &c) < 0)
1637 443d6288 2012-02-19 rsc if(c == 0x63){
1638 443d6288 2012-02-19 rsc if(ip->rex&REXW)
1639 443d6288 2012-02-19 rsc op = &obase[0x100]; /* MOVLQSX */
1641 443d6288 2012-02-19 rsc op = &obase[0x101]; /* MOVLQZX */
1645 a84cbb2a 2004-04-19 devnull op = &obase[c];
1647 a84cbb2a 2004-04-19 devnull if (op->proto == 0) {
1649 a84cbb2a 2004-04-19 devnull n = snprint(buf, sizeof(buf), "opcode: ??");
1650 a84cbb2a 2004-04-19 devnull for (i = 0; i < ip->n && n < sizeof(buf)-3; i++, n+=2)
1651 a84cbb2a 2004-04-19 devnull _hexify(buf+n, ip->mem[i], 1);
1652 a84cbb2a 2004-04-19 devnull strcpy(buf+n, "??");
1653 a84cbb2a 2004-04-19 devnull werrstr(buf);
1654 a84cbb2a 2004-04-19 devnull return 0;
1656 a84cbb2a 2004-04-19 devnull for(i = 0; i < 2 && op->operand[i]; i++) {
1657 443d6288 2012-02-19 rsc switch(op->operand[i]) {
1658 a84cbb2a 2004-04-19 devnull case Ib: /* 8-bit immediate - (no sign extension)*/
1659 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1660 a84cbb2a 2004-04-19 devnull return 0;
1661 a84cbb2a 2004-04-19 devnull ip->imm = c&0xff;
1662 443d6288 2012-02-19 rsc ip->imm64 = ip->imm;
1664 a84cbb2a 2004-04-19 devnull case Jbs: /* 8-bit jump immediate (sign extended) */
1665 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1666 a84cbb2a 2004-04-19 devnull return 0;
1667 a84cbb2a 2004-04-19 devnull if (c&0x80)
1668 a84cbb2a 2004-04-19 devnull ip->imm = c|0xffffff00;
1670 a84cbb2a 2004-04-19 devnull ip->imm = c&0xff;
1671 443d6288 2012-02-19 rsc ip->imm64 = (int32)ip->imm;
1672 a84cbb2a 2004-04-19 devnull ip->jumptype = Jbs;
1674 a84cbb2a 2004-04-19 devnull case Ibs: /* 8-bit immediate (sign extended) */
1675 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1676 a84cbb2a 2004-04-19 devnull return 0;
1677 a84cbb2a 2004-04-19 devnull if (c&0x80)
1678 a84cbb2a 2004-04-19 devnull if (ip->osize == 'L')
1679 a84cbb2a 2004-04-19 devnull ip->imm = c|0xffffff00;
1681 a84cbb2a 2004-04-19 devnull ip->imm = c|0xff00;
1683 a84cbb2a 2004-04-19 devnull ip->imm = c&0xff;
1684 443d6288 2012-02-19 rsc ip->imm64 = (int32)ip->imm;
1686 a84cbb2a 2004-04-19 devnull case Iw: /* 16-bit immediate -> imm */
1687 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s) < 0)
1688 a84cbb2a 2004-04-19 devnull return 0;
1689 a84cbb2a 2004-04-19 devnull ip->imm = s&0xffff;
1690 443d6288 2012-02-19 rsc ip->imm64 = ip->imm;
1691 a84cbb2a 2004-04-19 devnull ip->jumptype = Iw;
1693 a84cbb2a 2004-04-19 devnull case Iw2: /* 16-bit immediate -> in imm2*/
1694 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s) < 0)
1695 a84cbb2a 2004-04-19 devnull return 0;
1696 a84cbb2a 2004-04-19 devnull ip->imm2 = s&0xffff;
1698 443d6288 2012-02-19 rsc case Iwd: /* Operand-sized immediate (no sign extension unless 64 bits)*/
1699 443d6288 2012-02-19 rsc if (ip->osize == 'L') {
1700 443d6288 2012-02-19 rsc if (igetl(map, ip, &ip->imm) < 0)
1702 443d6288 2012-02-19 rsc ip->imm64 = ip->imm;
1703 443d6288 2012-02-19 rsc if(ip->rex&REXW && (ip->imm & (1<<31)) != 0)
1704 310ae033 2017-01-06 rsc ip->imm64 |= (vlong)(~0ULL << 32);
1706 443d6288 2012-02-19 rsc if (igets(map, ip, &s)< 0)
1708 443d6288 2012-02-19 rsc ip->imm = s&0xffff;
1709 443d6288 2012-02-19 rsc ip->imm64 = ip->imm;
1712 443d6288 2012-02-19 rsc case Iwdq: /* Operand-sized immediate, possibly big */
1713 a84cbb2a 2004-04-19 devnull if (ip->osize == 'L') {
1714 a84cbb2a 2004-04-19 devnull if (igetl(map, ip, &ip->imm) < 0)
1715 a84cbb2a 2004-04-19 devnull return 0;
1716 443d6288 2012-02-19 rsc ip->imm64 = ip->imm;
1717 443d6288 2012-02-19 rsc if (ip->rex & REXW) {
1719 443d6288 2012-02-19 rsc if (igetl(map, ip, &l) < 0)
1721 443d6288 2012-02-19 rsc ip->imm64 |= (uvlong)l << 32;
1723 a84cbb2a 2004-04-19 devnull } else {
1724 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s)< 0)
1725 a84cbb2a 2004-04-19 devnull return 0;
1726 a84cbb2a 2004-04-19 devnull ip->imm = s&0xffff;
1729 a84cbb2a 2004-04-19 devnull case Awd: /* Address-sized immediate (no sign extension)*/
1730 a84cbb2a 2004-04-19 devnull if (ip->asize == 'E') {
1731 a84cbb2a 2004-04-19 devnull if (igetl(map, ip, &ip->imm) < 0)
1732 a84cbb2a 2004-04-19 devnull return 0;
1733 443d6288 2012-02-19 rsc /* TO DO: REX */
1734 a84cbb2a 2004-04-19 devnull } else {
1735 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s)< 0)
1736 a84cbb2a 2004-04-19 devnull return 0;
1737 a84cbb2a 2004-04-19 devnull ip->imm = s&0xffff;
1740 a84cbb2a 2004-04-19 devnull case Iwds: /* Operand-sized immediate (sign extended) */
1741 a84cbb2a 2004-04-19 devnull if (ip->osize == 'L') {
1742 a84cbb2a 2004-04-19 devnull if (igetl(map, ip, &ip->imm) < 0)
1743 a84cbb2a 2004-04-19 devnull return 0;
1744 a84cbb2a 2004-04-19 devnull } else {
1745 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s)< 0)
1746 a84cbb2a 2004-04-19 devnull return 0;
1747 a84cbb2a 2004-04-19 devnull if (s&0x8000)
1748 a84cbb2a 2004-04-19 devnull ip->imm = s|0xffff0000;
1750 a84cbb2a 2004-04-19 devnull ip->imm = s&0xffff;
1752 a84cbb2a 2004-04-19 devnull ip->jumptype = Iwds;
1754 a84cbb2a 2004-04-19 devnull case OA: /* literal 0x0a byte */
1755 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1756 a84cbb2a 2004-04-19 devnull return 0;
1757 a84cbb2a 2004-04-19 devnull if (c != 0x0a)
1758 a84cbb2a 2004-04-19 devnull goto badop;
1760 443d6288 2012-02-19 rsc case Op_R0: /* base register must be R0 */
1761 a84cbb2a 2004-04-19 devnull if (ip->base != 0)
1762 a84cbb2a 2004-04-19 devnull goto badop;
1764 443d6288 2012-02-19 rsc case Op_R1: /* base register must be R1 */
1765 a84cbb2a 2004-04-19 devnull if (ip->base != 1)
1766 a84cbb2a 2004-04-19 devnull goto badop;
1768 a84cbb2a 2004-04-19 devnull case RMB: /* R/M field with byte register (/r)*/
1769 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1770 a84cbb2a 2004-04-19 devnull return 0;
1771 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1772 a84cbb2a 2004-04-19 devnull return 0;
1773 a84cbb2a 2004-04-19 devnull ip->osize = 'B';
1775 a84cbb2a 2004-04-19 devnull case RM: /* R/M field with register (/r) */
1776 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1777 a84cbb2a 2004-04-19 devnull return 0;
1778 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1779 a84cbb2a 2004-04-19 devnull return 0;
1781 a84cbb2a 2004-04-19 devnull case RMOPB: /* R/M field with op code (/digit) */
1782 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1783 a84cbb2a 2004-04-19 devnull return 0;
1784 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1785 a84cbb2a 2004-04-19 devnull return 0;
1786 a84cbb2a 2004-04-19 devnull c = ip->reg; /* secondary op code */
1787 a84cbb2a 2004-04-19 devnull obase = (Optable*)op->proto;
1788 a84cbb2a 2004-04-19 devnull ip->osize = 'B';
1789 a84cbb2a 2004-04-19 devnull goto newop;
1790 a84cbb2a 2004-04-19 devnull case RMOP: /* R/M field with op code (/digit) */
1791 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1792 a84cbb2a 2004-04-19 devnull return 0;
1793 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1794 a84cbb2a 2004-04-19 devnull return 0;
1795 a84cbb2a 2004-04-19 devnull obase = (Optable*)op->proto;
1796 443d6288 2012-02-19 rsc if(ip->amd64 && obase == optab0F01 && c == 0xF8)
1797 443d6288 2012-02-19 rsc return optab0F01F8;
1798 443d6288 2012-02-19 rsc c = ip->reg;
1799 a84cbb2a 2004-04-19 devnull goto newop;
1800 a84cbb2a 2004-04-19 devnull case FRMOP: /* FP R/M field with op code (/digit) */
1801 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1802 a84cbb2a 2004-04-19 devnull return 0;
1803 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1804 a84cbb2a 2004-04-19 devnull return 0;
1805 a84cbb2a 2004-04-19 devnull if ((c&0xc0) == 0xc0)
1806 a84cbb2a 2004-04-19 devnull c = ip->reg+8; /* 16 entry table */
1808 a84cbb2a 2004-04-19 devnull c = ip->reg;
1809 a84cbb2a 2004-04-19 devnull obase = (Optable*)op->proto;
1810 a84cbb2a 2004-04-19 devnull goto newop;
1811 a84cbb2a 2004-04-19 devnull case FRMEX: /* Extended FP R/M field with op code (/digit) */
1812 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1813 a84cbb2a 2004-04-19 devnull return 0;
1814 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1815 a84cbb2a 2004-04-19 devnull return 0;
1816 a84cbb2a 2004-04-19 devnull if ((c&0xc0) == 0xc0)
1817 a84cbb2a 2004-04-19 devnull c = (c&0x3f)+8; /* 64-entry table */
1819 a84cbb2a 2004-04-19 devnull c = ip->reg;
1820 a84cbb2a 2004-04-19 devnull obase = (Optable*)op->proto;
1821 a84cbb2a 2004-04-19 devnull goto newop;
1822 a84cbb2a 2004-04-19 devnull case RMR: /* R/M register only (mod = 11) */
1823 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1824 a84cbb2a 2004-04-19 devnull return 0;
1825 a84cbb2a 2004-04-19 devnull if ((c&0xc0) != 0xc0) {
1826 a84cbb2a 2004-04-19 devnull werrstr("invalid R/M register: %x", c);
1827 a84cbb2a 2004-04-19 devnull return 0;
1829 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1830 a84cbb2a 2004-04-19 devnull return 0;
1832 a84cbb2a 2004-04-19 devnull case RMM: /* R/M register only (mod = 11) */
1833 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1834 a84cbb2a 2004-04-19 devnull return 0;
1835 a84cbb2a 2004-04-19 devnull if ((c&0xc0) == 0xc0) {
1836 a84cbb2a 2004-04-19 devnull werrstr("invalid R/M memory mode: %x", c);
1837 a84cbb2a 2004-04-19 devnull return 0;
1839 a84cbb2a 2004-04-19 devnull if (modrm(map, ip, c) < 0)
1840 a84cbb2a 2004-04-19 devnull return 0;
1842 a84cbb2a 2004-04-19 devnull case PTR: /* Seg:Displacement addr (ptr16:16 or ptr16:32) */
1843 a84cbb2a 2004-04-19 devnull if (ip->osize == 'L') {
1844 a84cbb2a 2004-04-19 devnull if (igetl(map, ip, &ip->disp) < 0)
1845 a84cbb2a 2004-04-19 devnull return 0;
1846 a84cbb2a 2004-04-19 devnull } else {
1847 a84cbb2a 2004-04-19 devnull if (igets(map, ip, &s)< 0)
1848 a84cbb2a 2004-04-19 devnull return 0;
1849 a84cbb2a 2004-04-19 devnull ip->disp = s&0xffff;
1851 a84cbb2a 2004-04-19 devnull if (igets(map, ip, (ushort*)&ip->seg) < 0)
1852 a84cbb2a 2004-04-19 devnull return 0;
1853 a84cbb2a 2004-04-19 devnull ip->jumptype = PTR;
1855 443d6288 2012-02-19 rsc case AUXMM: /* Multi-byte op code; prefix determines table selection */
1856 443d6288 2012-02-19 rsc if (igetc(map, ip, &c) < 0)
1858 443d6288 2012-02-19 rsc obase = (Optable*)op->proto;
1859 443d6288 2012-02-19 rsc switch (ip->opre) {
1860 443d6288 2012-02-19 rsc case 0x66: op = optab660F; break;
1861 443d6288 2012-02-19 rsc case 0xF2: op = optabF20F; break;
1862 443d6288 2012-02-19 rsc case 0xF3: op = optabF30F; break;
1863 443d6288 2012-02-19 rsc default: op = nil; break;
1865 443d6288 2012-02-19 rsc if(op != nil && op[c].proto != nil)
1866 443d6288 2012-02-19 rsc obase = op;
1867 443d6288 2012-02-19 rsc norex = 1; /* no more rex prefixes */
1868 443d6288 2012-02-19 rsc /* otherwise the optab entry captures it */
1869 443d6288 2012-02-19 rsc goto newop;
1870 a84cbb2a 2004-04-19 devnull case AUX: /* Multi-byte op code - Auxiliary table */
1871 a84cbb2a 2004-04-19 devnull obase = (Optable*)op->proto;
1872 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1873 a84cbb2a 2004-04-19 devnull return 0;
1874 a84cbb2a 2004-04-19 devnull goto newop;
1875 443d6288 2012-02-19 rsc case OPRE: /* Instr Prefix or media op */
1876 443d6288 2012-02-19 rsc ip->opre = c;
1877 443d6288 2012-02-19 rsc /* fall through */
1878 a84cbb2a 2004-04-19 devnull case PRE: /* Instr Prefix */
1879 a84cbb2a 2004-04-19 devnull ip->prefix = (char*)op->proto;
1880 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1881 a84cbb2a 2004-04-19 devnull return 0;
1882 443d6288 2012-02-19 rsc if (ip->opre && c == 0x0F)
1883 443d6288 2012-02-19 rsc ip->prefix = 0;
1884 a84cbb2a 2004-04-19 devnull goto newop;
1885 a84cbb2a 2004-04-19 devnull case SEG: /* Segment Prefix */
1886 a84cbb2a 2004-04-19 devnull ip->segment = (char*)op->proto;
1887 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1888 a84cbb2a 2004-04-19 devnull return 0;
1889 a84cbb2a 2004-04-19 devnull goto newop;
1890 a84cbb2a 2004-04-19 devnull case OPOVER: /* Operand size override */
1891 443d6288 2012-02-19 rsc ip->opre = c;
1892 a84cbb2a 2004-04-19 devnull ip->osize = 'W';
1893 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1894 a84cbb2a 2004-04-19 devnull return 0;
1895 443d6288 2012-02-19 rsc if (c == 0x0F)
1896 443d6288 2012-02-19 rsc ip->osize = 'L';
1897 443d6288 2012-02-19 rsc else if (ip->amd64 && (c&0xF0) == 0x40)
1898 443d6288 2012-02-19 rsc ip->osize = 'Q';
1899 a84cbb2a 2004-04-19 devnull goto newop;
1900 a84cbb2a 2004-04-19 devnull case ADDOVER: /* Address size override */
1901 a84cbb2a 2004-04-19 devnull ip->asize = 0;
1902 a84cbb2a 2004-04-19 devnull if (igetc(map, ip, &c) < 0)
1903 a84cbb2a 2004-04-19 devnull return 0;
1904 a84cbb2a 2004-04-19 devnull goto newop;
1905 a84cbb2a 2004-04-19 devnull case JUMP: /* mark instruction as JUMP or RET */
1906 a84cbb2a 2004-04-19 devnull case RET:
1907 a84cbb2a 2004-04-19 devnull ip->jumptype = op->operand[i];
1909 a84cbb2a 2004-04-19 devnull default:
1910 a84cbb2a 2004-04-19 devnull werrstr("bad operand type %d", op->operand[i]);
1911 a84cbb2a 2004-04-19 devnull return 0;
1914 a84cbb2a 2004-04-19 devnull return op;
1917 443d6288 2012-02-19 rsc #pragma varargck argpos bprint 2
1919 a84cbb2a 2004-04-19 devnull static void
1920 a84cbb2a 2004-04-19 devnull bprint(Instr *ip, char *fmt, ...)
1922 a84cbb2a 2004-04-19 devnull va_list arg;
1924 a84cbb2a 2004-04-19 devnull va_start(arg, fmt);
1925 a84cbb2a 2004-04-19 devnull ip->curr = vseprint(ip->curr, ip->end, fmt, arg);
1926 a84cbb2a 2004-04-19 devnull va_end(arg);
1930 a84cbb2a 2004-04-19 devnull * if we want to call 16 bit regs AX,BX,CX,...
1931 a84cbb2a 2004-04-19 devnull * and 32 bit regs EAX,EBX,ECX,... then
1932 a84cbb2a 2004-04-19 devnull * change the defs of ANAME and ONAME to:
1933 a84cbb2a 2004-04-19 devnull * #define ANAME(ip) ((ip->asize == 'E' ? "E" : "")
1934 a84cbb2a 2004-04-19 devnull * #define ONAME(ip) ((ip)->osize == 'L' ? "E" : "")
1936 a84cbb2a 2004-04-19 devnull #define ANAME(ip) ""
1937 a84cbb2a 2004-04-19 devnull #define ONAME(ip) ""
1939 a84cbb2a 2004-04-19 devnull static char *reg[] = {
1940 443d6288 2012-02-19 rsc [AX] = "AX",
1941 443d6288 2012-02-19 rsc [CX] = "CX",
1942 443d6288 2012-02-19 rsc [DX] = "DX",
1943 443d6288 2012-02-19 rsc [BX] = "BX",
1944 443d6288 2012-02-19 rsc [SP] = "SP",
1945 443d6288 2012-02-19 rsc [BP] = "BP",
1946 443d6288 2012-02-19 rsc [SI] = "SI",
1947 443d6288 2012-02-19 rsc [DI] = "DI",
1949 443d6288 2012-02-19 rsc /* amd64 */
1950 443d6288 2012-02-19 rsc [AMD64_R8] = "R8",
1951 443d6288 2012-02-19 rsc [AMD64_R9] = "R9",
1952 443d6288 2012-02-19 rsc [AMD64_R10] = "R10",
1953 443d6288 2012-02-19 rsc [AMD64_R11] = "R11",
1954 443d6288 2012-02-19 rsc [AMD64_R12] = "R12",
1955 443d6288 2012-02-19 rsc [AMD64_R13] = "R13",
1956 443d6288 2012-02-19 rsc [AMD64_R14] = "R14",
1957 443d6288 2012-02-19 rsc [AMD64_R15] = "R15",
1960 a84cbb2a 2004-04-19 devnull static char *breg[] = { "AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH" };
1961 443d6288 2012-02-19 rsc static char *breg64[] = { "AL", "CL", "DL", "BL", "SPB", "BPB", "SIB", "DIB",
1962 443d6288 2012-02-19 rsc "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B" };
1963 a84cbb2a 2004-04-19 devnull static char *sreg[] = { "ES", "CS", "SS", "DS", "FS", "GS" };
1965 a84cbb2a 2004-04-19 devnull static void
1966 a84cbb2a 2004-04-19 devnull plocal(Instr *ip)
1968 a84cbb2a 2004-04-19 devnull Symbol s;
1969 a84cbb2a 2004-04-19 devnull char *name;
1970 a84cbb2a 2004-04-19 devnull Loc l, li;
1972 a84cbb2a 2004-04-19 devnull l.type = LOFFSET;
1973 a84cbb2a 2004-04-19 devnull l.offset = ip->disp;
1974 a84cbb2a 2004-04-19 devnull if(ip->base == SP)
1975 a84cbb2a 2004-04-19 devnull l.reg = "SP";
1977 a84cbb2a 2004-04-19 devnull l.reg = "BP";
1979 a84cbb2a 2004-04-19 devnull li.type = LADDR;
1980 a84cbb2a 2004-04-19 devnull li.addr = ip->addr;
1981 a84cbb2a 2004-04-19 devnull if(findsym(li, CTEXT, &s) < 0)
1982 a84cbb2a 2004-04-19 devnull goto raw;
1984 a84cbb2a 2004-04-19 devnull name = nil;
1985 443d6288 2012-02-19 rsc if(ip->base==SP && lookuplsym(&s, FRAMENAME, &s) >= 0) {
1986 443d6288 2012-02-19 rsc /* translate stack offset to offset from plan 9 frame pointer*/
1987 a84cbb2a 2004-04-19 devnull /* XXX not sure how to do this */
1990 a84cbb2a 2004-04-19 devnull if(name==nil && findlsym(&s, l, &s) >= 0)
1991 a84cbb2a 2004-04-19 devnull name = s.name;
1993 a84cbb2a 2004-04-19 devnull if(name)
1994 a84cbb2a 2004-04-19 devnull bprint(ip, "%s+", name);
1997 443d6288 2012-02-19 rsc bprint(ip, "%#lx(%s)", l.offset, l.reg);
1999 443d6288 2012-02-19 rsc if (s.value > ip->disp) {
2000 443d6288 2012-02-19 rsc ret = getauto(&s, s.value-ip->disp-mach->szaddr, CAUTO, &s);
2001 443d6288 2012-02-19 rsc reg = "(SP)";
2003 443d6288 2012-02-19 rsc offset -= s.value;
2004 443d6288 2012-02-19 rsc ret = getauto(&s, offset, CPARAM, &s);
2005 443d6288 2012-02-19 rsc reg = "(FP)";
2008 443d6288 2012-02-19 rsc bprint(ip, "%s+", s.name);
2010 443d6288 2012-02-19 rsc offset = ip->disp;
2011 443d6288 2012-02-19 rsc bprint(ip, "%ux%s", offset, reg);
2015 a84cbb2a 2004-04-19 devnull static int
2016 a84cbb2a 2004-04-19 devnull isjmp(Instr *ip)
2018 a84cbb2a 2004-04-19 devnull switch(ip->jumptype){
2019 a84cbb2a 2004-04-19 devnull case Iwds:
2020 a84cbb2a 2004-04-19 devnull case Jbs:
2021 a84cbb2a 2004-04-19 devnull case JUMP:
2022 a84cbb2a 2004-04-19 devnull return 1;
2023 a84cbb2a 2004-04-19 devnull default:
2024 a84cbb2a 2004-04-19 devnull return 0;
2029 a84cbb2a 2004-04-19 devnull * This is too smart for its own good, but it really is nice
2030 a84cbb2a 2004-04-19 devnull * to have accurate translations when debugging, and it
2031 a84cbb2a 2004-04-19 devnull * helps us identify which code is different in binaries that
2032 a84cbb2a 2004-04-19 devnull * are changed on sources.
2034 a84cbb2a 2004-04-19 devnull static int
2035 443d6288 2012-02-19 rsc issymref(Instr *ip, Symbol *s, int32 w, int32 val)
2037 a84cbb2a 2004-04-19 devnull Symbol next, tmp;
2038 443d6288 2012-02-19 rsc int32 isstring, size;
2040 a84cbb2a 2004-04-19 devnull if (isjmp(ip))
2041 a84cbb2a 2004-04-19 devnull return 1;
2042 a84cbb2a 2004-04-19 devnull if (s->class==CTEXT && w==0)
2043 a84cbb2a 2004-04-19 devnull return 1;
2044 a84cbb2a 2004-04-19 devnull if (s->class==CDATA) {
2045 a84cbb2a 2004-04-19 devnull /* use first bss symbol (or "end") rather than edata */
2046 a84cbb2a 2004-04-19 devnull if (s->name[0]=='e' && strcmp(s->name, "edata") == 0){
2047 443d6288 2012-02-19 rsc if((indexsym(s->index+1, &tmp) && loccmp(&tmp.loc, &s->loc) == 0)
2048 443d6288 2012-02-19 rsc || (indexsym(s->index-1, &tmp) && loccmp(&tmp.loc, &s->loc) == 0))
2049 a84cbb2a 2004-04-19 devnull *s = tmp;
2051 a84cbb2a 2004-04-19 devnull if (w == 0)
2052 a84cbb2a 2004-04-19 devnull return 1;
2053 a84cbb2a 2004-04-19 devnull for (next=*s; next.loc.addr==s->loc.addr; next=tmp)
2054 a84cbb2a 2004-04-19 devnull if (!indexsym(next.index+1, &tmp))
2056 a84cbb2a 2004-04-19 devnull size = next.loc.addr - s->loc.addr;
2057 a84cbb2a 2004-04-19 devnull if (w >= size)
2058 a84cbb2a 2004-04-19 devnull return 0;
2059 a84cbb2a 2004-04-19 devnull if (w > size-w)
2060 a84cbb2a 2004-04-19 devnull w = size-w;
2061 a84cbb2a 2004-04-19 devnull /* huge distances are usually wrong except in .string */
2062 a84cbb2a 2004-04-19 devnull isstring = (s->name[0]=='.' && strcmp(s->name, ".string") == 0);
2063 a84cbb2a 2004-04-19 devnull if (w > 8192 && !isstring)
2064 a84cbb2a 2004-04-19 devnull return 0;
2065 a84cbb2a 2004-04-19 devnull /* medium distances are tricky - look for constants */
2066 a84cbb2a 2004-04-19 devnull /* near powers of two */
2067 a84cbb2a 2004-04-19 devnull if ((val&(val-1)) == 0 || (val&(val+1)) == 0)
2068 a84cbb2a 2004-04-19 devnull return 0;
2069 a84cbb2a 2004-04-19 devnull return 1;
2071 a84cbb2a 2004-04-19 devnull return 0;
2074 a84cbb2a 2004-04-19 devnull static void
2075 443d6288 2012-02-19 rsc immediate(Instr *ip, vlong val)
2077 a84cbb2a 2004-04-19 devnull Symbol s;
2078 a84cbb2a 2004-04-19 devnull long w;
2081 a84cbb2a 2004-04-19 devnull l.type = LADDR;
2082 a84cbb2a 2004-04-19 devnull l.addr = val;
2083 443d6288 2012-02-19 rsc if (findsym(l, CANY, &s) >= 0) { /* TO DO */
2084 a84cbb2a 2004-04-19 devnull w = val - s.loc.addr;
2085 a84cbb2a 2004-04-19 devnull if (w < 0)
2086 a84cbb2a 2004-04-19 devnull w = -w;
2087 a84cbb2a 2004-04-19 devnull if (issymref(ip, &s, w, val)) {
2089 443d6288 2012-02-19 rsc bprint(ip, "%s+%#lux(SB)", s.name, w);
2091 a84cbb2a 2004-04-19 devnull bprint(ip, "%s(SB)", s.name);
2092 a84cbb2a 2004-04-19 devnull return;
2095 443d6288 2012-02-19 rsc if (s.class==CDATA && globalsym(&s, s.index+1)) {
2096 443d6288 2012-02-19 rsc w = s.value - val;
2097 a84cbb2a 2004-04-19 devnull if (w < 0)
2098 a84cbb2a 2004-04-19 devnull w = -w;
2099 a84cbb2a 2004-04-19 devnull if (w < 4096) {
2100 443d6288 2012-02-19 rsc bprint(ip, "%s-%#lux(SB)", s.name, w);
2101 a84cbb2a 2004-04-19 devnull return;
2106 443d6288 2012-02-19 rsc if((ip->rex & REXW) == 0)
2107 443d6288 2012-02-19 rsc bprint(ip, "%lux", (long)val);
2109 443d6288 2012-02-19 rsc bprint(ip, "%llux", val);
2112 a84cbb2a 2004-04-19 devnull static void
2113 a84cbb2a 2004-04-19 devnull pea(Instr *ip)
2115 a84cbb2a 2004-04-19 devnull if (ip->mod == 3) {
2116 a84cbb2a 2004-04-19 devnull if (ip->osize == 'B')
2117 443d6288 2012-02-19 rsc bprint(ip, (ip->rex & REXB? breg64: breg)[(uchar)ip->base]);
2118 443d6288 2012-02-19 rsc else if(ip->rex & REXB)
2119 443d6288 2012-02-19 rsc bprint(ip, "%s%s", ANAME(ip), reg[ip->base+8]);
2121 a84cbb2a 2004-04-19 devnull bprint(ip, "%s%s", ANAME(ip), reg[(uchar)ip->base]);
2122 a84cbb2a 2004-04-19 devnull return;
2124 a84cbb2a 2004-04-19 devnull if (ip->segment)
2125 a84cbb2a 2004-04-19 devnull bprint(ip, ip->segment);
2126 443d6288 2012-02-19 rsc if (ip->asize == 'E' && ip->base == SP)
2127 a84cbb2a 2004-04-19 devnull plocal(ip);
2129 a84cbb2a 2004-04-19 devnull if (ip->base < 0)
2130 a84cbb2a 2004-04-19 devnull immediate(ip, ip->disp);
2132 443d6288 2012-02-19 rsc bprint(ip, "%ux", ip->disp);
2133 443d6288 2012-02-19 rsc if(ip->rip)
2134 443d6288 2012-02-19 rsc bprint(ip, "(RIP)");
2135 443d6288 2012-02-19 rsc bprint(ip,"(%s%s)", ANAME(ip), reg[ip->rex&REXB? ip->base+8: ip->base]);
2138 a84cbb2a 2004-04-19 devnull if (ip->index >= 0)
2139 443d6288 2012-02-19 rsc bprint(ip,"(%s%s*%d)", ANAME(ip), reg[ip->rex&REXX? ip->index+8: ip->index], 1<<ip->ss);
2142 a84cbb2a 2004-04-19 devnull static void
2143 a84cbb2a 2004-04-19 devnull prinstr(Instr *ip, char *fmt)
2148 a84cbb2a 2004-04-19 devnull if (ip->prefix)
2149 a84cbb2a 2004-04-19 devnull bprint(ip, "%s ", ip->prefix);
2150 a84cbb2a 2004-04-19 devnull for (; *fmt && ip->curr < ip->end; fmt++) {
2151 443d6288 2012-02-19 rsc if (*fmt != '%'){
2152 a84cbb2a 2004-04-19 devnull *ip->curr++ = *fmt;
2156 443d6288 2012-02-19 rsc if(*++fmt == '#') {
2160 443d6288 2012-02-19 rsc switch(*fmt){
2161 a84cbb2a 2004-04-19 devnull case '%':
2162 a84cbb2a 2004-04-19 devnull *ip->curr++ = '%';
2164 a84cbb2a 2004-04-19 devnull case 'A':
2165 a84cbb2a 2004-04-19 devnull bprint(ip, "%s", ANAME(ip));
2167 a84cbb2a 2004-04-19 devnull case 'C':
2168 a84cbb2a 2004-04-19 devnull bprint(ip, "CR%d", ip->reg);
2170 a84cbb2a 2004-04-19 devnull case 'D':
2171 a84cbb2a 2004-04-19 devnull if (ip->reg < 4 || ip->reg == 6 || ip->reg == 7)
2172 a84cbb2a 2004-04-19 devnull bprint(ip, "DR%d",ip->reg);
2174 a84cbb2a 2004-04-19 devnull bprint(ip, "???");
2176 a84cbb2a 2004-04-19 devnull case 'I':
2177 a84cbb2a 2004-04-19 devnull bprint(ip, "$");
2178 a84cbb2a 2004-04-19 devnull immediate(ip, ip->imm2);
2180 a84cbb2a 2004-04-19 devnull case 'O':
2181 a84cbb2a 2004-04-19 devnull bprint(ip,"%s", ONAME(ip));
2183 a84cbb2a 2004-04-19 devnull case 'i':
2185 443d6288 2012-02-19 rsc bprint(ip, "$");
2186 443d6288 2012-02-19 rsc v = ip->imm;
2187 443d6288 2012-02-19 rsc if(ip->rex & REXW)
2188 443d6288 2012-02-19 rsc v = ip->imm64;
2189 443d6288 2012-02-19 rsc immediate(ip, v);
2191 a84cbb2a 2004-04-19 devnull case 'R':
2192 443d6288 2012-02-19 rsc bprint(ip, "%s%s", ONAME(ip), reg[ip->rex&REXR? ip->reg+8: ip->reg]);
2194 a84cbb2a 2004-04-19 devnull case 'S':
2195 443d6288 2012-02-19 rsc if(ip->osize == 'Q' || ip->osize == 'L' && ip->rex & REXW)
2196 443d6288 2012-02-19 rsc bprint(ip, "Q");
2198 443d6288 2012-02-19 rsc bprint(ip, "%c", ip->osize);
2201 443d6288 2012-02-19 rsc if(ip->opre == 0 || ip->opre == 0x66)
2202 443d6288 2012-02-19 rsc bprint(ip, "P");
2204 443d6288 2012-02-19 rsc bprint(ip, "S");
2205 443d6288 2012-02-19 rsc if(ip->opre == 0xf2 || ip->opre == 0x66)
2206 443d6288 2012-02-19 rsc bprint(ip, "D");
2208 443d6288 2012-02-19 rsc bprint(ip, "S");
2210 a84cbb2a 2004-04-19 devnull case 'T':
2211 a84cbb2a 2004-04-19 devnull if (ip->reg == 6 || ip->reg == 7)
2212 a84cbb2a 2004-04-19 devnull bprint(ip, "TR%d",ip->reg);
2214 a84cbb2a 2004-04-19 devnull bprint(ip, "???");
2217 443d6288 2012-02-19 rsc if (ip->osize == 'Q' || ip->osize == 'L' && ip->rex & REXW)
2218 443d6288 2012-02-19 rsc bprint(ip, "CDQE");
2219 443d6288 2012-02-19 rsc else if (ip->osize == 'L')
2220 a84cbb2a 2004-04-19 devnull bprint(ip,"CWDE");
2222 a84cbb2a 2004-04-19 devnull bprint(ip, "CBW");
2224 a84cbb2a 2004-04-19 devnull case 'd':
2225 443d6288 2012-02-19 rsc bprint(ip,"%ux:%ux", ip->seg, ip->disp);
2228 443d6288 2012-02-19 rsc if (ip->mod == 3 && ip->osize != 'B') {
2229 443d6288 2012-02-19 rsc if(fmt[1] != '*'){
2230 443d6288 2012-02-19 rsc if(ip->opre != 0) {
2231 443d6288 2012-02-19 rsc bprint(ip, "X%d", ip->rex&REXB? ip->base+8: ip->base);
2236 443d6288 2012-02-19 rsc bprint(ip, "M%d", ip->base);
2241 a84cbb2a 2004-04-19 devnull case 'e':
2242 a84cbb2a 2004-04-19 devnull pea(ip);
2244 a84cbb2a 2004-04-19 devnull case 'f':
2245 a84cbb2a 2004-04-19 devnull bprint(ip, "F%d", ip->base);
2247 a84cbb2a 2004-04-19 devnull case 'g':
2248 a84cbb2a 2004-04-19 devnull if (ip->reg < 6)
2249 a84cbb2a 2004-04-19 devnull bprint(ip,"%s",sreg[ip->reg]);
2251 a84cbb2a 2004-04-19 devnull bprint(ip,"???");
2253 a84cbb2a 2004-04-19 devnull case 'p':
2255 443d6288 2012-02-19 rsc * signed immediate in the uint32 ip->imm.
2257 443d6288 2012-02-19 rsc v = (int32)ip->imm;
2258 443d6288 2012-02-19 rsc immediate(ip, v+ip->addr+ip->n);
2260 a84cbb2a 2004-04-19 devnull case 'r':
2261 a84cbb2a 2004-04-19 devnull if (ip->osize == 'B')
2262 443d6288 2012-02-19 rsc bprint(ip,"%s", (ip->rex? breg64: breg)[ip->rex&REXR? ip->reg+8: ip->reg]);
2264 443d6288 2012-02-19 rsc bprint(ip, reg[ip->rex&REXR? ip->reg+8: ip->reg]);
2267 443d6288 2012-02-19 rsc if (ip->osize == 'Q' || ip->rex & REXW)
2268 443d6288 2012-02-19 rsc bprint(ip, "CQO");
2269 443d6288 2012-02-19 rsc else if (ip->osize == 'L')
2270 a84cbb2a 2004-04-19 devnull bprint(ip,"CDQ");
2272 a84cbb2a 2004-04-19 devnull bprint(ip, "CWD");
2275 443d6288 2012-02-19 rsc if(ip->opre != 0)
2276 443d6288 2012-02-19 rsc bprint(ip, "X%d", ip->rex&REXR? ip->reg+8: ip->reg);
2278 443d6288 2012-02-19 rsc bprint(ip, "M%d", ip->reg);
2281 443d6288 2012-02-19 rsc if (ip->mod == 3 && ip->osize != 'B') {
2282 443d6288 2012-02-19 rsc bprint(ip, "X%d", ip->rex&REXB? ip->base+8: ip->base);
2288 443d6288 2012-02-19 rsc bprint(ip, "X%d", ip->rex&REXR? ip->reg+8: ip->reg);
2290 a84cbb2a 2004-04-19 devnull default:
2291 a84cbb2a 2004-04-19 devnull bprint(ip, "%%%c", *fmt);
2295 a84cbb2a 2004-04-19 devnull *ip->curr = 0; /* there's always room for 1 byte */
2299 443d6288 2012-02-19 rsc i386das(Map *map, uvlong pc, char modifier, char *buf, int n)
2301 443d6288 2012-02-19 rsc Instr instr;
2302 a84cbb2a 2004-04-19 devnull Optable *op;
2304 a84cbb2a 2004-04-19 devnull USED(modifier);
2305 a84cbb2a 2004-04-19 devnull op = mkinstr(map, &instr, pc);
2306 a84cbb2a 2004-04-19 devnull if (op == 0) {
2307 a84cbb2a 2004-04-19 devnull errstr(buf, n);
2308 a84cbb2a 2004-04-19 devnull return -1;
2310 a84cbb2a 2004-04-19 devnull instr.curr = buf;
2311 a84cbb2a 2004-04-19 devnull instr.end = buf+n-1;
2312 a84cbb2a 2004-04-19 devnull prinstr(&instr, op->proto);
2313 a84cbb2a 2004-04-19 devnull return instr.n;
2317 443d6288 2012-02-19 rsc i386hexinst(Map *map, u64int pc, char *buf, int n)
2319 443d6288 2012-02-19 rsc Instr instr;
2322 a84cbb2a 2004-04-19 devnull if (mkinstr(map, &instr, pc) == 0) {
2323 a84cbb2a 2004-04-19 devnull errstr(buf, n);
2324 a84cbb2a 2004-04-19 devnull return -1;
2326 a84cbb2a 2004-04-19 devnull for(i = 0; i < instr.n && n > 2; i++) {
2327 a84cbb2a 2004-04-19 devnull _hexify(buf, instr.mem[i], 1);
2328 a84cbb2a 2004-04-19 devnull buf += 2;
2329 a84cbb2a 2004-04-19 devnull n -= 2;
2331 a84cbb2a 2004-04-19 devnull *buf = 0;
2332 a84cbb2a 2004-04-19 devnull return instr.n;
2336 443d6288 2012-02-19 rsc i386instlen(Map *map, u64int pc)
2338 a84cbb2a 2004-04-19 devnull Instr i;
2340 a84cbb2a 2004-04-19 devnull if (mkinstr(map, &i, pc))
2341 a84cbb2a 2004-04-19 devnull return i.n;
2342 a84cbb2a 2004-04-19 devnull return -1;
2346 443d6288 2012-02-19 rsc i386foll(Map *map, Regs *regs, u64int pc, u64int *foll)
2348 a84cbb2a 2004-04-19 devnull Instr i;
2349 a84cbb2a 2004-04-19 devnull Optable *op;
2350 a84cbb2a 2004-04-19 devnull ushort s;
2351 443d6288 2012-02-19 rsc u64int l, addr;
2355 a84cbb2a 2004-04-19 devnull op = mkinstr(map, &i, pc);
2356 a84cbb2a 2004-04-19 devnull if (!op)
2357 a84cbb2a 2004-04-19 devnull return -1;
2361 a84cbb2a 2004-04-19 devnull switch(i.jumptype) {
2362 a84cbb2a 2004-04-19 devnull case RET: /* RETURN or LEAVE */
2363 a84cbb2a 2004-04-19 devnull case Iw: /* RETURN */
2364 a84cbb2a 2004-04-19 devnull if (strcmp(op->proto, "LEAVE") == 0) {
2365 443d6288 2012-02-19 rsc if (lgeta(map, regs, locindir("BP", 0), &l) < 0)
2366 a84cbb2a 2004-04-19 devnull return -1;
2367 443d6288 2012-02-19 rsc } else if (lgeta(map, regs, locindir(mach->sp, 0), &l) < 0)
2368 a84cbb2a 2004-04-19 devnull return -1;
2369 a84cbb2a 2004-04-19 devnull foll[0] = l;
2370 a84cbb2a 2004-04-19 devnull return 1;
2371 a84cbb2a 2004-04-19 devnull case Iwds: /* pc relative JUMP or CALL*/
2372 a84cbb2a 2004-04-19 devnull case Jbs: /* pc relative JUMP or CALL */
2373 443d6288 2012-02-19 rsc v = (int32)i.imm;
2374 443d6288 2012-02-19 rsc foll[0] = pc+v+i.n;
2377 a84cbb2a 2004-04-19 devnull case PTR: /* seg:displacement JUMP or CALL */
2378 a84cbb2a 2004-04-19 devnull foll[0] = (i.seg<<4)+i.disp;
2379 a84cbb2a 2004-04-19 devnull return 1;
2380 a84cbb2a 2004-04-19 devnull case JUMP: /* JUMP or CALL EA */
2382 a84cbb2a 2004-04-19 devnull if(i.mod == 3) {
2383 443d6288 2012-02-19 rsc if (rget(regs, reg[i.rex&REXB? i.base+8: i.base], &foll[0]) < 0)
2384 a84cbb2a 2004-04-19 devnull return -1;
2385 a84cbb2a 2004-04-19 devnull return 1;
2387 a84cbb2a 2004-04-19 devnull /* calculate the effective address */
2388 a84cbb2a 2004-04-19 devnull addr = i.disp;
2389 a84cbb2a 2004-04-19 devnull if (i.base >= 0) {
2390 443d6288 2012-02-19 rsc if (lgeta(map, regs, locindir(reg[i.rex&REXB? i.base+8: i.base], 0), &l) < 0)
2391 a84cbb2a 2004-04-19 devnull return -1;
2392 a84cbb2a 2004-04-19 devnull addr += l;
2394 a84cbb2a 2004-04-19 devnull if (i.index >= 0) {
2395 443d6288 2012-02-19 rsc if (lgeta(map, regs, locindir(reg[i.rex&REXX? i.index+8: i.index], 0), &l) < 0)
2396 a84cbb2a 2004-04-19 devnull return -1;
2397 a84cbb2a 2004-04-19 devnull addr += l*(1<<i.ss);
2399 a84cbb2a 2004-04-19 devnull /* now retrieve a seg:disp value at that address */
2400 443d6288 2012-02-19 rsc if (get2(map, addr, &s) < 0) /* seg */
2401 a84cbb2a 2004-04-19 devnull return -1;
2402 a84cbb2a 2004-04-19 devnull foll[0] = s<<4;
2403 a84cbb2a 2004-04-19 devnull addr += 2;
2404 a84cbb2a 2004-04-19 devnull if (i.asize == 'L') {
2405 443d6288 2012-02-19 rsc if (geta(map, addr, &l) < 0) /* disp32 */
2406 a84cbb2a 2004-04-19 devnull return -1;
2407 a84cbb2a 2004-04-19 devnull foll[0] += l;
2408 a84cbb2a 2004-04-19 devnull } else { /* disp16 */
2409 a84cbb2a 2004-04-19 devnull if (get2(map, addr, &s) < 0)
2410 a84cbb2a 2004-04-19 devnull return -1;
2411 a84cbb2a 2004-04-19 devnull foll[0] += s;
2413 a84cbb2a 2004-04-19 devnull return 1;
2414 a84cbb2a 2004-04-19 devnull default:
2417 a84cbb2a 2004-04-19 devnull if (strncmp(op->proto,"JMP", 3) == 0 || strncmp(op->proto,"CALL", 4) == 0)
2418 a84cbb2a 2004-04-19 devnull return 1;
2419 a84cbb2a 2004-04-19 devnull foll[n++] = pc+i.n;
2420 a84cbb2a 2004-04-19 devnull return n;
