1 443d6288 2012-02-19 rsc // Inferno libmach/6.c
2 443d6288 2012-02-19 rsc // http://code.google.com/p/inferno-os/source/browse/utils/libmach/6.c
4 443d6288 2012-02-19 rsc // Copyright © 1994-1999 Lucent Technologies Inc.
5 443d6288 2012-02-19 rsc // Power PC support Copyright © 1995-2004 C H Forsyth (forsyth@terzarima.net).
6 443d6288 2012-02-19 rsc // Portions Copyright © 1997-1999 Vita Nuova Limited.
7 443d6288 2012-02-19 rsc // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com).
8 443d6288 2012-02-19 rsc // Revisions Copyright © 2000-2004 Lucent Technologies Inc. and others.
9 443d6288 2012-02-19 rsc // Portions Copyright © 2009 The Go Authors. All rights reserved.
11 443d6288 2012-02-19 rsc // Permission is hereby granted, free of charge, to any person obtaining a copy
12 443d6288 2012-02-19 rsc // of this software and associated documentation files (the "Software"), to deal
13 443d6288 2012-02-19 rsc // in the Software without restriction, including without limitation the rights
14 443d6288 2012-02-19 rsc // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 443d6288 2012-02-19 rsc // copies of the Software, and to permit persons to whom the Software is
16 443d6288 2012-02-19 rsc // furnished to do so, subject to the following conditions:
18 443d6288 2012-02-19 rsc // The above copyright notice and this permission notice shall be included in
19 443d6288 2012-02-19 rsc // all copies or substantial portions of the Software.
21 443d6288 2012-02-19 rsc // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 443d6288 2012-02-19 rsc // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 443d6288 2012-02-19 rsc // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
24 443d6288 2012-02-19 rsc // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 443d6288 2012-02-19 rsc // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 443d6288 2012-02-19 rsc // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 443d6288 2012-02-19 rsc // THE SOFTWARE.
30 443d6288 2012-02-19 rsc * amd64 definition
32 443d6288 2012-02-19 rsc #include <u.h>
33 443d6288 2012-02-19 rsc #include <libc.h>
34 443d6288 2012-02-19 rsc #include <bio.h>
35 443d6288 2012-02-19 rsc #include <mach.h>
36 443d6288 2012-02-19 rsc #include "uregamd64.h"
38 443d6288 2012-02-19 rsc char *i386excep(Map*, Regs*);
39 443d6288 2012-02-19 rsc int i386foll(Map*, Regs*, u64int, u64int*);
40 443d6288 2012-02-19 rsc int i386hexinst(Map*, u64int, char*, int);
41 443d6288 2012-02-19 rsc int i386das(Map*, u64int, char, char*, int);
42 443d6288 2012-02-19 rsc int i386instlen(Map*, u64int);
43 443d6288 2012-02-19 rsc int i386unwind(Map*, Regs*, u64int*, Symbol*);
45 443d6288 2012-02-19 rsc #define REGOFF(x) offsetof(struct Ureg, x)
47 443d6288 2012-02-19 rsc #define REGSIZE sizeof(struct Ureg)
48 443d6288 2012-02-19 rsc #define FP_CTLS(x) (REGSIZE+2*(x))
49 443d6288 2012-02-19 rsc #define FP_CTL(x) (REGSIZE+4*(x))
50 443d6288 2012-02-19 rsc #define FP_REG(x) (FP_CTL(8)+16*(x))
51 443d6288 2012-02-19 rsc #define XM_REG(x) (FP_CTL(8)+8*16+16*(x))
53 443d6288 2012-02-19 rsc #define FPREGSIZE 512 /* TO DO? currently only 0x1A0 used */
55 443d6288 2012-02-19 rsc static Regdesc amd64reglist[] = {
56 443d6288 2012-02-19 rsc {"AX", REGOFF(ax), RINT, 'Y'},
57 443d6288 2012-02-19 rsc {"BX", REGOFF(bx), RINT, 'Y'},
58 443d6288 2012-02-19 rsc {"CX", REGOFF(cx), RINT, 'Y'},
59 443d6288 2012-02-19 rsc {"DX", REGOFF(dx), RINT, 'Y'},
60 443d6288 2012-02-19 rsc {"SI", REGOFF(si), RINT, 'Y'},
61 443d6288 2012-02-19 rsc {"DI", REGOFF(di), RINT, 'Y'},
62 443d6288 2012-02-19 rsc {"BP", REGOFF(bp), RINT, 'Y'},
63 443d6288 2012-02-19 rsc {"R8", REGOFF(r8), RINT, 'Y'},
64 443d6288 2012-02-19 rsc {"R9", REGOFF(r9), RINT, 'Y'},
65 443d6288 2012-02-19 rsc {"R10", REGOFF(r10), RINT, 'Y'},
66 443d6288 2012-02-19 rsc {"R11", REGOFF(r11), RINT, 'Y'},
67 443d6288 2012-02-19 rsc {"R12", REGOFF(r12), RINT, 'Y'},
68 443d6288 2012-02-19 rsc {"R13", REGOFF(r13), RINT, 'Y'},
69 443d6288 2012-02-19 rsc {"R14", REGOFF(r14), RINT, 'Y'},
70 443d6288 2012-02-19 rsc {"R15", REGOFF(r15), RINT, 'Y'},
71 443d6288 2012-02-19 rsc {"DS", REGOFF(ds), RINT, 'x'},
72 443d6288 2012-02-19 rsc {"ES", REGOFF(es), RINT, 'x'},
73 443d6288 2012-02-19 rsc {"FS", REGOFF(fs), RINT, 'x'},
74 443d6288 2012-02-19 rsc {"GS", REGOFF(gs), RINT, 'x'},
75 443d6288 2012-02-19 rsc {"TYPE", REGOFF(type), RINT, 'Y'},
76 443d6288 2012-02-19 rsc {"TRAP", REGOFF(type), RINT, 'Y'}, /* alias for acid */
77 443d6288 2012-02-19 rsc {"ERROR", REGOFF(error), RINT, 'Y'},
78 443d6288 2012-02-19 rsc {"IP", REGOFF(ip), RINT, 'Y'},
79 443d6288 2012-02-19 rsc {"PC", REGOFF(ip), RINT, 'Y'}, /* alias for acid */
80 443d6288 2012-02-19 rsc {"CS", REGOFF(cs), RINT, 'Y'},
81 443d6288 2012-02-19 rsc {"FLAGS", REGOFF(flags), RINT, 'Y'},
82 443d6288 2012-02-19 rsc {"SP", REGOFF(sp), RINT, 'Y'},
83 443d6288 2012-02-19 rsc {"SS", REGOFF(ss), RINT, 'Y'},
85 443d6288 2012-02-19 rsc {"FCW", FP_CTLS(0), RFLT, 'x'},
86 443d6288 2012-02-19 rsc {"FSW", FP_CTLS(1), RFLT, 'x'},
87 443d6288 2012-02-19 rsc {"FTW", FP_CTLS(2), RFLT, 'b'},
88 443d6288 2012-02-19 rsc {"FOP", FP_CTLS(3), RFLT, 'x'},
89 443d6288 2012-02-19 rsc {"RIP", FP_CTL(2), RFLT, 'Y'},
90 443d6288 2012-02-19 rsc {"RDP", FP_CTL(4), RFLT, 'Y'},
91 443d6288 2012-02-19 rsc {"MXCSR", FP_CTL(6), RFLT, 'X'},
92 443d6288 2012-02-19 rsc {"MXCSRMASK", FP_CTL(7), RFLT, 'X'},
93 443d6288 2012-02-19 rsc {"M0", FP_REG(0), RFLT, 'F'}, /* assumes double */
94 443d6288 2012-02-19 rsc {"M1", FP_REG(1), RFLT, 'F'},
95 443d6288 2012-02-19 rsc {"M2", FP_REG(2), RFLT, 'F'},
96 443d6288 2012-02-19 rsc {"M3", FP_REG(3), RFLT, 'F'},
97 443d6288 2012-02-19 rsc {"M4", FP_REG(4), RFLT, 'F'},
98 443d6288 2012-02-19 rsc {"M5", FP_REG(5), RFLT, 'F'},
99 443d6288 2012-02-19 rsc {"M6", FP_REG(6), RFLT, 'F'},
100 443d6288 2012-02-19 rsc {"M7", FP_REG(7), RFLT, 'F'},
101 443d6288 2012-02-19 rsc {"X0", XM_REG(0), RFLT, 'F'}, /* assumes double */
102 443d6288 2012-02-19 rsc {"X1", XM_REG(1), RFLT, 'F'},
103 443d6288 2012-02-19 rsc {"X2", XM_REG(2), RFLT, 'F'},
104 443d6288 2012-02-19 rsc {"X3", XM_REG(3), RFLT, 'F'},
105 443d6288 2012-02-19 rsc {"X4", XM_REG(4), RFLT, 'F'},
106 443d6288 2012-02-19 rsc {"X5", XM_REG(5), RFLT, 'F'},
107 443d6288 2012-02-19 rsc {"X6", XM_REG(6), RFLT, 'F'},
108 443d6288 2012-02-19 rsc {"X7", XM_REG(7), RFLT, 'F'},
109 443d6288 2012-02-19 rsc {"X8", XM_REG(8), RFLT, 'F'},
110 443d6288 2012-02-19 rsc {"X9", XM_REG(9), RFLT, 'F'},
111 443d6288 2012-02-19 rsc {"X10", XM_REG(10), RFLT, 'F'},
112 443d6288 2012-02-19 rsc {"X11", XM_REG(11), RFLT, 'F'},
113 443d6288 2012-02-19 rsc {"X12", XM_REG(12), RFLT, 'F'},
114 443d6288 2012-02-19 rsc {"X13", XM_REG(13), RFLT, 'F'},
115 443d6288 2012-02-19 rsc {"X14", XM_REG(14), RFLT, 'F'},
116 443d6288 2012-02-19 rsc {"X15", XM_REG(15), RFLT, 'F'},
117 443d6288 2012-02-19 rsc {"X16", XM_REG(16), RFLT, 'F'},
119 443d6288 2012-02-19 rsc {"F0", FP_REG(7), RFLT, '3'},
120 443d6288 2012-02-19 rsc {"F1", FP_REG(6), RFLT, '3'},
121 443d6288 2012-02-19 rsc {"F2", FP_REG(5), RFLT, '3'},
122 443d6288 2012-02-19 rsc {"F3", FP_REG(4), RFLT, '3'},
123 443d6288 2012-02-19 rsc {"F4", FP_REG(3), RFLT, '3'},
124 443d6288 2012-02-19 rsc {"F5", FP_REG(2), RFLT, '3'},
125 443d6288 2012-02-19 rsc {"F6", FP_REG(1), RFLT, '3'},
126 443d6288 2012-02-19 rsc {"F7", FP_REG(0), RFLT, '3'},
131 443d6288 2012-02-19 rsc static char *amd64windregs[] = {
153 443d6288 2012-02-19 rsc Mach machamd64=
156 443d6288 2012-02-19 rsc MAMD64, /* machine type */
157 443d6288 2012-02-19 rsc amd64reglist, /* register list */
158 443d6288 2012-02-19 rsc REGSIZE, /* size of registers in bytes */
159 443d6288 2012-02-19 rsc FPREGSIZE, /* size of fp registers in bytes */
160 443d6288 2012-02-19 rsc "PC", /* name of PC */
161 443d6288 2012-02-19 rsc "SP", /* name of SP */
162 443d6288 2012-02-19 rsc "BP", /* name of FP */
163 443d6288 2012-02-19 rsc 0, /* link register */
164 443d6288 2012-02-19 rsc "setSB", /* static base register name (bogus anyways) */
165 443d6288 2012-02-19 rsc 0, /* static base register value */
166 443d6288 2012-02-19 rsc 0x1000, /* page size */
167 443d6288 2012-02-19 rsc 0xFFFFFFFF80110000ULL, /* kernel base */
168 443d6288 2012-02-19 rsc 0xFFFF800000000000ULL, /* kernel text mask */
169 443d6288 2012-02-19 rsc 1, /* quantization of pc */
170 443d6288 2012-02-19 rsc 8, /* szaddr */
171 443d6288 2012-02-19 rsc 4, /* szreg */
172 443d6288 2012-02-19 rsc 4, /* szfloat */
173 443d6288 2012-02-19 rsc 8, /* szdouble */
175 443d6288 2012-02-19 rsc amd64windregs, /* locations unwound in stack trace */
178 443d6288 2012-02-19 rsc {0xCC, 0, 0, 0}, /* break point: INT 3 */
179 443d6288 2012-02-19 rsc 1, /* break point size */
181 443d6288 2012-02-19 rsc i386foll, /* following addresses */
182 443d6288 2012-02-19 rsc i386excep, /* print exception */
183 443d6288 2012-02-19 rsc i386unwind, /* stack unwind */
185 443d6288 2012-02-19 rsc leswap2, /* convert short to local byte order */
186 443d6288 2012-02-19 rsc leswap4, /* convert long to local byte order */
187 443d6288 2012-02-19 rsc leswap8, /* convert vlong to local byte order */
188 443d6288 2012-02-19 rsc leieeeftoa32, /* single precision float pointer */
189 443d6288 2012-02-19 rsc leieeeftoa64, /* double precision float pointer */
190 443d6288 2012-02-19 rsc leieeeftoa80, /* long double precision floating point */
192 443d6288 2012-02-19 rsc i386das, /* dissembler */
193 443d6288 2012-02-19 rsc i386das, /* plan9-format disassembler */
194 443d6288 2012-02-19 rsc 0, /* commercial disassembler */
195 443d6288 2012-02-19 rsc i386hexinst, /* print instruction */
196 443d6288 2012-02-19 rsc i386instlen, /* instruction size calculation */
