1 a84cbb2a 2004-04-19 devnull #include <u.h>
  2 a84cbb2a 2004-04-19 devnull #include <libc.h>
  3 a84cbb2a 2004-04-19 devnull #include <mach.h>
  4 a84cbb2a 2004-04-19 devnull #include "macho.h"
  5 a84cbb2a 2004-04-19 devnull #include "uregpower.h"
  6 a84cbb2a 2004-04-19 devnull 
  7 a84cbb2a 2004-04-19 devnull enum
  8 a84cbb2a 2004-04-19 devnull {
  9 a84cbb2a 2004-04-19 devnull 	ThreadState = 1,
 10 a84cbb2a 2004-04-19 devnull 	FloatState,
 11 a84cbb2a 2004-04-19 devnull 	ExceptionState,
 12 a84cbb2a 2004-04-19 devnull 	VectorState,
 13 a84cbb2a 2004-04-19 devnull 	ThreadState64,
 14 a84cbb2a 2004-04-19 devnull 	ExceptionState64,
 15 cbeb0b26 2006-04-01 devnull 	ThreadStateNone
 16 a84cbb2a 2004-04-19 devnull };
 17 a84cbb2a 2004-04-19 devnull 
 18 a84cbb2a 2004-04-19 devnull typedef struct Lreg Lreg;
 19 a84cbb2a 2004-04-19 devnull typedef struct Lflt Lflt;
 20 a84cbb2a 2004-04-19 devnull typedef struct Lexc Lexc;
 21 a84cbb2a 2004-04-19 devnull 
 22 a84cbb2a 2004-04-19 devnull struct Lreg
 23 a84cbb2a 2004-04-19 devnull {
 24 a84cbb2a 2004-04-19 devnull 	u32int srr0;
 25 a84cbb2a 2004-04-19 devnull 	u32int srr1;
 26 a84cbb2a 2004-04-19 devnull 	u32int r0;
 27 a84cbb2a 2004-04-19 devnull 	u32int r1;
 28 a84cbb2a 2004-04-19 devnull 	u32int r2;
 29 a84cbb2a 2004-04-19 devnull 	u32int r3;
 30 a84cbb2a 2004-04-19 devnull 	u32int r4;
 31 a84cbb2a 2004-04-19 devnull 	u32int r5;
 32 a84cbb2a 2004-04-19 devnull 	u32int r6;
 33 a84cbb2a 2004-04-19 devnull 	u32int r7;
 34 a84cbb2a 2004-04-19 devnull 	u32int r8;
 35 a84cbb2a 2004-04-19 devnull 	u32int r9;
 36 a84cbb2a 2004-04-19 devnull 	u32int r10;
 37 a84cbb2a 2004-04-19 devnull 	u32int r11;
 38 a84cbb2a 2004-04-19 devnull 	u32int r12;
 39 a84cbb2a 2004-04-19 devnull 	u32int r13;
 40 a84cbb2a 2004-04-19 devnull 	u32int r14;
 41 a84cbb2a 2004-04-19 devnull 	u32int r15;
 42 a84cbb2a 2004-04-19 devnull 	u32int r16;
 43 a84cbb2a 2004-04-19 devnull 	u32int r17;
 44 a84cbb2a 2004-04-19 devnull 	u32int r18;
 45 a84cbb2a 2004-04-19 devnull 	u32int r19;
 46 a84cbb2a 2004-04-19 devnull 	u32int r20;
 47 a84cbb2a 2004-04-19 devnull 	u32int r21;
 48 a84cbb2a 2004-04-19 devnull 	u32int r22;
 49 a84cbb2a 2004-04-19 devnull 	u32int r23;
 50 a84cbb2a 2004-04-19 devnull 	u32int r24;
 51 a84cbb2a 2004-04-19 devnull 	u32int r25;
 52 a84cbb2a 2004-04-19 devnull 	u32int r26;
 53 a84cbb2a 2004-04-19 devnull 	u32int r27;
 54 a84cbb2a 2004-04-19 devnull 	u32int r28;
 55 a84cbb2a 2004-04-19 devnull 	u32int r29;
 56 a84cbb2a 2004-04-19 devnull 	u32int r30;
 57 a84cbb2a 2004-04-19 devnull 	u32int r31;
 58 a84cbb2a 2004-04-19 devnull 
 59 a84cbb2a 2004-04-19 devnull 	u32int cr;
 60 a84cbb2a 2004-04-19 devnull 	u32int xer;
 61 a84cbb2a 2004-04-19 devnull 	u32int lr;
 62 a84cbb2a 2004-04-19 devnull 	u32int ctr;
 63 a84cbb2a 2004-04-19 devnull 	u32int mq;
 64 a84cbb2a 2004-04-19 devnull 
 65 a84cbb2a 2004-04-19 devnull 	u32int vrsave;
 66 a84cbb2a 2004-04-19 devnull };
 67 a84cbb2a 2004-04-19 devnull 
 68 a84cbb2a 2004-04-19 devnull struct Lflt
 69 a84cbb2a 2004-04-19 devnull {
 70 a84cbb2a 2004-04-19 devnull 	u32int fpregs[32*2];		/* 32 doubles */
 71 a84cbb2a 2004-04-19 devnull 	u32int fpscr[2];
 72 a84cbb2a 2004-04-19 devnull 
 73 a84cbb2a 2004-04-19 devnull };
 74 a84cbb2a 2004-04-19 devnull 
 75 a84cbb2a 2004-04-19 devnull struct Lexc
 76 a84cbb2a 2004-04-19 devnull {
 77 a84cbb2a 2004-04-19 devnull 	u32int dar;
 78 a84cbb2a 2004-04-19 devnull 	u32int dsisr;
 79 a84cbb2a 2004-04-19 devnull 	u32int exception;
 80 a84cbb2a 2004-04-19 devnull 	u32int pad0;
 81 a84cbb2a 2004-04-19 devnull 	u32int pad1[4];
 82 a84cbb2a 2004-04-19 devnull };
 83 a84cbb2a 2004-04-19 devnull 
 84 a84cbb2a 2004-04-19 devnull static void
 85 a84cbb2a 2004-04-19 devnull lreg2ureg(Lreg *l, Ureg *u)
 86 a84cbb2a 2004-04-19 devnull {
 87 a84cbb2a 2004-04-19 devnull 	u->pc = l->srr0;
 88 a84cbb2a 2004-04-19 devnull 	u->srr1 = l->srr1;
 89 a84cbb2a 2004-04-19 devnull 	u->lr = l->lr;
 90 a84cbb2a 2004-04-19 devnull 	u->cr = l->cr;
 91 a84cbb2a 2004-04-19 devnull 	u->xer = l->xer;
 92 a84cbb2a 2004-04-19 devnull 	u->ctr = l->ctr;
 93 a84cbb2a 2004-04-19 devnull 	u->vrsave = l->vrsave;
 94 a84cbb2a 2004-04-19 devnull 	memmove(&u->r0, &l->r0, 32*4);
 95 a84cbb2a 2004-04-19 devnull }
 96 a84cbb2a 2004-04-19 devnull 
 97 a84cbb2a 2004-04-19 devnull static void
 98 a84cbb2a 2004-04-19 devnull lexc2ureg(Lexc *l, Ureg *u)
 99 a84cbb2a 2004-04-19 devnull {
100 a84cbb2a 2004-04-19 devnull 	u->cause = l->exception;
101 a84cbb2a 2004-04-19 devnull 	u->dar = l->dar;
102 a84cbb2a 2004-04-19 devnull 	u->dsisr = l->dsisr;
103 a84cbb2a 2004-04-19 devnull }
104 a84cbb2a 2004-04-19 devnull 
105 a84cbb2a 2004-04-19 devnull static uchar*
106 a84cbb2a 2004-04-19 devnull load(int fd, ulong off, int size)
107 a84cbb2a 2004-04-19 devnull {
108 a84cbb2a 2004-04-19 devnull 	uchar *a;
109 a84cbb2a 2004-04-19 devnull 
110 a84cbb2a 2004-04-19 devnull 	a = malloc(size);
111 a84cbb2a 2004-04-19 devnull 	if(a == nil)
112 a84cbb2a 2004-04-19 devnull 		return nil;
113 a84cbb2a 2004-04-19 devnull 	if(seek(fd, off, 0) < 0 || readn(fd, a, size) != size){
114 a84cbb2a 2004-04-19 devnull 		free(a);
115 a84cbb2a 2004-04-19 devnull 		return nil;
116 a84cbb2a 2004-04-19 devnull 	}
117 a84cbb2a 2004-04-19 devnull 	return a;
118 a84cbb2a 2004-04-19 devnull }
119 a84cbb2a 2004-04-19 devnull 
120 a84cbb2a 2004-04-19 devnull int
121 a84cbb2a 2004-04-19 devnull coreregsmachopower(Macho *m, uchar **up)
122 a84cbb2a 2004-04-19 devnull {
123 a84cbb2a 2004-04-19 devnull 	int i, havereg, haveexc;
124 a84cbb2a 2004-04-19 devnull 	uchar *a, *p, *nextp;
125 a84cbb2a 2004-04-19 devnull 	Ureg *u;
126 a84cbb2a 2004-04-19 devnull 	ulong flavor, count;
127 a84cbb2a 2004-04-19 devnull 	MachoCmd *c;
128 a84cbb2a 2004-04-19 devnull 
129 a84cbb2a 2004-04-19 devnull 	*up = nil;
130 a84cbb2a 2004-04-19 devnull 	for(i=0; i<m->ncmd; i++)
131 a84cbb2a 2004-04-19 devnull 		if(m->cmd[i].type == MachoCmdThread)
132 a84cbb2a 2004-04-19 devnull 			break;
133 a84cbb2a 2004-04-19 devnull 	if(i == m->ncmd){
134 a84cbb2a 2004-04-19 devnull 		werrstr("no registers found");
135 a84cbb2a 2004-04-19 devnull 		return -1;
136 a84cbb2a 2004-04-19 devnull 	}
137 a84cbb2a 2004-04-19 devnull 
138 a84cbb2a 2004-04-19 devnull 	c = &m->cmd[i];
139 a84cbb2a 2004-04-19 devnull 	a = load(m->fd, c->off, c->size);
140 a84cbb2a 2004-04-19 devnull 	if(a == nil)
141 a84cbb2a 2004-04-19 devnull 		return -1;
142 a84cbb2a 2004-04-19 devnull 
143 a84cbb2a 2004-04-19 devnull 	if((u = mallocz(sizeof(Ureg), 1)) == nil){
144 a84cbb2a 2004-04-19 devnull 		free(a);
145 a84cbb2a 2004-04-19 devnull 		return -1;
146 a84cbb2a 2004-04-19 devnull 	}
147 a84cbb2a 2004-04-19 devnull 
148 a84cbb2a 2004-04-19 devnull 	havereg = haveexc = 0;
149 a84cbb2a 2004-04-19 devnull 	for(p=a+8; p<a+c->size; p=nextp){
150 a84cbb2a 2004-04-19 devnull 		flavor = m->e4(p);
151 a84cbb2a 2004-04-19 devnull 		count = m->e4(p+4);
152 a84cbb2a 2004-04-19 devnull 		nextp = p+8+count*4;
153 a84cbb2a 2004-04-19 devnull 		if(flavor == ThreadState && count*4 == sizeof(Lreg)){
154 a84cbb2a 2004-04-19 devnull 			havereg = 1;
155 a84cbb2a 2004-04-19 devnull 			lreg2ureg((Lreg*)(p+8), u);
156 a84cbb2a 2004-04-19 devnull 		}
157 a84cbb2a 2004-04-19 devnull 		if(flavor == ExceptionState && count*4 == sizeof(Lexc)){
158 a84cbb2a 2004-04-19 devnull 			haveexc = 1;
159 a84cbb2a 2004-04-19 devnull 			lexc2ureg((Lexc*)(p+8), u);
160 a84cbb2a 2004-04-19 devnull 		}
161 a84cbb2a 2004-04-19 devnull 	}
162 a84cbb2a 2004-04-19 devnull 	free(a);
163 a84cbb2a 2004-04-19 devnull 	if(!havereg){
164 a84cbb2a 2004-04-19 devnull 		werrstr("no registers found");
165 a84cbb2a 2004-04-19 devnull 		free(u);
166 a84cbb2a 2004-04-19 devnull 		return -1;
167 a84cbb2a 2004-04-19 devnull 	}
168 a84cbb2a 2004-04-19 devnull 	if(!haveexc)
169 a84cbb2a 2004-04-19 devnull 		fprint(2, "warning: no exception state in core file registers\n");
170 a84cbb2a 2004-04-19 devnull 	*up = (uchar*)u;
171 a84cbb2a 2004-04-19 devnull 	return sizeof(*u);
172 a84cbb2a 2004-04-19 devnull }