2 a84cbb2a 2004-04-19 devnull * PowerPC definition
3 a84cbb2a 2004-04-19 devnull * forsyth@plan9.cs.york.ac.uk
5 a84cbb2a 2004-04-19 devnull #include <u.h>
6 a84cbb2a 2004-04-19 devnull #include <libc.h>
7 a84cbb2a 2004-04-19 devnull #include <bio.h>
8 a84cbb2a 2004-04-19 devnull #include "uregpower.h"
9 a84cbb2a 2004-04-19 devnull #include <mach.h>
12 a84cbb2a 2004-04-19 devnull * PowerPC-specific debugger interface
13 a84cbb2a 2004-04-19 devnull * forsyth@plan9.cs.york.ac.uk
16 a84cbb2a 2004-04-19 devnull static char *powerexcep(Map*, Regs*);
17 443d6288 2012-02-19 rsc static int powerfoll(Map*, Regs*, u64int, u64int*);
18 443d6288 2012-02-19 rsc static int powerdas(Map*, u64int, char, char*, int);
19 443d6288 2012-02-19 rsc static int powerinstlen(Map*, u64int);
20 443d6288 2012-02-19 rsc static int powerhexinst(Map*, u64int, char*, int);
22 a84cbb2a 2004-04-19 devnull static char *excname[] =
24 a84cbb2a 2004-04-19 devnull "reserved 0",
25 a84cbb2a 2004-04-19 devnull "system reset",
26 a84cbb2a 2004-04-19 devnull "machine check",
27 a84cbb2a 2004-04-19 devnull "data access",
28 a84cbb2a 2004-04-19 devnull "instruction access",
29 a84cbb2a 2004-04-19 devnull "external interrupt",
30 a84cbb2a 2004-04-19 devnull "alignment",
31 a84cbb2a 2004-04-19 devnull "program exception",
32 a84cbb2a 2004-04-19 devnull "floating-point unavailable",
33 a84cbb2a 2004-04-19 devnull "decrementer",
34 a84cbb2a 2004-04-19 devnull "i/o controller interface error",
35 a84cbb2a 2004-04-19 devnull "reserved B",
36 a84cbb2a 2004-04-19 devnull "system call",
37 a84cbb2a 2004-04-19 devnull "trace trap",
38 a84cbb2a 2004-04-19 devnull "floating point assist",
39 a84cbb2a 2004-04-19 devnull "reserved",
40 a84cbb2a 2004-04-19 devnull "ITLB miss",
41 a84cbb2a 2004-04-19 devnull "DTLB load miss",
42 a84cbb2a 2004-04-19 devnull "DTLB store miss",
43 a84cbb2a 2004-04-19 devnull "instruction address breakpoint"
44 a84cbb2a 2004-04-19 devnull "SMI interrupt"
45 a84cbb2a 2004-04-19 devnull "reserved 15",
46 a84cbb2a 2004-04-19 devnull "reserved 16",
47 a84cbb2a 2004-04-19 devnull "reserved 17",
48 a84cbb2a 2004-04-19 devnull "reserved 18",
49 a84cbb2a 2004-04-19 devnull "reserved 19",
50 a84cbb2a 2004-04-19 devnull "reserved 1A",
51 a84cbb2a 2004-04-19 devnull /* the following are made up on a program exception */
52 a84cbb2a 2004-04-19 devnull "floating point exception", /* FPEXC */
53 a84cbb2a 2004-04-19 devnull "illegal instruction",
54 a84cbb2a 2004-04-19 devnull "privileged instruction",
56 a84cbb2a 2004-04-19 devnull "illegal operation",
59 a84cbb2a 2004-04-19 devnull static char*
60 a84cbb2a 2004-04-19 devnull powerexcep(Map *map, Regs *regs)
63 a84cbb2a 2004-04-19 devnull static char buf[32];
65 a84cbb2a 2004-04-19 devnull if(rget(regs, "CAUSE", &c) < 0)
66 a84cbb2a 2004-04-19 devnull return "no cause register";
68 a84cbb2a 2004-04-19 devnull if(c < nelem(excname))
69 a84cbb2a 2004-04-19 devnull return excname[c];
70 a84cbb2a 2004-04-19 devnull sprint(buf, "unknown trap #%lux", c);
71 a84cbb2a 2004-04-19 devnull return buf;
75 a84cbb2a 2004-04-19 devnull * disassemble PowerPC opcodes
78 a84cbb2a 2004-04-19 devnull #define REGSP 1 /* should come from q.out.h, but there's a clash */
79 a84cbb2a 2004-04-19 devnull #define REGSB 2
81 cbeb0b26 2006-04-01 devnull /*static char FRAMENAME[] = ".frame"; */
83 a84cbb2a 2004-04-19 devnull static Map *mymap;
86 a84cbb2a 2004-04-19 devnull * ibm conventions for these: bit 0 is top bit
87 a84cbb2a 2004-04-19 devnull * from table 10-1
89 a84cbb2a 2004-04-19 devnull typedef struct {
90 a84cbb2a 2004-04-19 devnull uchar aa; /* bit 30 */
91 a84cbb2a 2004-04-19 devnull uchar crba; /* bits 11-15 */
92 a84cbb2a 2004-04-19 devnull uchar crbb; /* bits 16-20 */
93 a84cbb2a 2004-04-19 devnull long bd; /* bits 16-29 */
94 a84cbb2a 2004-04-19 devnull uchar crfd; /* bits 6-8 */
95 a84cbb2a 2004-04-19 devnull uchar crfs; /* bits 11-13 */
96 a84cbb2a 2004-04-19 devnull uchar bi; /* bits 11-15 */
97 a84cbb2a 2004-04-19 devnull uchar bo; /* bits 6-10 */
98 a84cbb2a 2004-04-19 devnull uchar crbd; /* bits 6-10 */
99 70e24710 2004-04-19 devnull /*union {*/
100 a84cbb2a 2004-04-19 devnull short d; /* bits 16-31 */
101 a84cbb2a 2004-04-19 devnull short simm;
102 a84cbb2a 2004-04-19 devnull ushort uimm;
104 a84cbb2a 2004-04-19 devnull uchar fm; /* bits 7-14 */
105 a84cbb2a 2004-04-19 devnull uchar fra; /* bits 11-15 */
106 a84cbb2a 2004-04-19 devnull uchar frb; /* bits 16-20 */
107 a84cbb2a 2004-04-19 devnull uchar frc; /* bits 21-25 */
108 a84cbb2a 2004-04-19 devnull uchar frs; /* bits 6-10 */
109 a84cbb2a 2004-04-19 devnull uchar frd; /* bits 6-10 */
110 a84cbb2a 2004-04-19 devnull uchar crm; /* bits 12-19 */
111 a84cbb2a 2004-04-19 devnull long li; /* bits 6-29 || b'00' */
112 a84cbb2a 2004-04-19 devnull uchar lk; /* bit 31 */
113 a84cbb2a 2004-04-19 devnull uchar mb; /* bits 21-25 */
114 a84cbb2a 2004-04-19 devnull uchar me; /* bits 26-30 */
115 a84cbb2a 2004-04-19 devnull uchar nb; /* bits 16-20 */
116 a84cbb2a 2004-04-19 devnull uchar op; /* bits 0-5 */
117 a84cbb2a 2004-04-19 devnull uchar oe; /* bit 21 */
118 a84cbb2a 2004-04-19 devnull uchar ra; /* bits 11-15 */
119 a84cbb2a 2004-04-19 devnull uchar rb; /* bits 16-20 */
120 a84cbb2a 2004-04-19 devnull uchar rc; /* bit 31 */
121 70e24710 2004-04-19 devnull /*union {*/
122 a84cbb2a 2004-04-19 devnull uchar rs; /* bits 6-10 */
123 a84cbb2a 2004-04-19 devnull uchar rd;
125 a84cbb2a 2004-04-19 devnull uchar sh; /* bits 16-20 */
126 a84cbb2a 2004-04-19 devnull ushort spr; /* bits 11-20 */
127 a84cbb2a 2004-04-19 devnull uchar to; /* bits 6-10 */
128 a84cbb2a 2004-04-19 devnull uchar imm; /* bits 16-19 */
129 a84cbb2a 2004-04-19 devnull ushort xo; /* bits 21-30, 22-30, 26-30, or 30 (beware) */
130 a84cbb2a 2004-04-19 devnull long immediate;
131 a84cbb2a 2004-04-19 devnull long w0;
132 a84cbb2a 2004-04-19 devnull long w1;
133 443d6288 2012-02-19 rsc u64int addr; /* pc of instruction */
134 a84cbb2a 2004-04-19 devnull short target;
135 a84cbb2a 2004-04-19 devnull char *curr; /* current fill level in output buffer */
136 a84cbb2a 2004-04-19 devnull char *end; /* end of buffer */
137 a84cbb2a 2004-04-19 devnull int size; /* number of longs in instr */
138 a84cbb2a 2004-04-19 devnull char *err; /* errmsg */
139 a84cbb2a 2004-04-19 devnull } Instr;
141 310ae033 2017-01-06 rsc #define IBF(v,a,b) (((ulong)(v)>>(32-(b)-1)) & ~(~0UL<<(((b)-(a)+1))))
142 a84cbb2a 2004-04-19 devnull #define IB(v,b) IBF((v),(b),(b))
144 a84cbb2a 2004-04-19 devnull static void
145 a84cbb2a 2004-04-19 devnull bprint(Instr *i, char *fmt, ...)
147 a84cbb2a 2004-04-19 devnull va_list arg;
149 a84cbb2a 2004-04-19 devnull va_start(arg, fmt);
150 a84cbb2a 2004-04-19 devnull i->curr = vseprint(i->curr, i->end, fmt, arg);
151 a84cbb2a 2004-04-19 devnull va_end(arg);
154 a84cbb2a 2004-04-19 devnull static int
155 a84cbb2a 2004-04-19 devnull decode(ulong pc, Instr *i)
157 a84cbb2a 2004-04-19 devnull u32int w;
159 a84cbb2a 2004-04-19 devnull if (get4(mymap, pc, &w) < 0) {
160 a84cbb2a 2004-04-19 devnull werrstr("can't read instruction: %r");
161 a84cbb2a 2004-04-19 devnull return -1;
163 a84cbb2a 2004-04-19 devnull i->aa = IB(w, 30);
164 a84cbb2a 2004-04-19 devnull i->crba = IBF(w, 11, 15);
165 a84cbb2a 2004-04-19 devnull i->crbb = IBF(w, 16, 20);
166 a84cbb2a 2004-04-19 devnull i->bd = IBF(w, 16, 29)<<2;
167 a84cbb2a 2004-04-19 devnull if(i->bd & 0x8000)
168 310ae033 2017-01-06 rsc i->bd |= ~0UL<<16;
169 a84cbb2a 2004-04-19 devnull i->crfd = IBF(w, 6, 8);
170 a84cbb2a 2004-04-19 devnull i->crfs = IBF(w, 11, 13);
171 a84cbb2a 2004-04-19 devnull i->bi = IBF(w, 11, 15);
172 a84cbb2a 2004-04-19 devnull i->bo = IBF(w, 6, 10);
173 a84cbb2a 2004-04-19 devnull i->crbd = IBF(w, 6, 10);
174 a84cbb2a 2004-04-19 devnull i->uimm = IBF(w, 16, 31); /* also d, simm */
175 a84cbb2a 2004-04-19 devnull i->fm = IBF(w, 7, 14);
176 a84cbb2a 2004-04-19 devnull i->fra = IBF(w, 11, 15);
177 a84cbb2a 2004-04-19 devnull i->frb = IBF(w, 16, 20);
178 a84cbb2a 2004-04-19 devnull i->frc = IBF(w, 21, 25);
179 a84cbb2a 2004-04-19 devnull i->frs = IBF(w, 6, 10);
180 a84cbb2a 2004-04-19 devnull i->frd = IBF(w, 6, 10);
181 a84cbb2a 2004-04-19 devnull i->crm = IBF(w, 12, 19);
182 a84cbb2a 2004-04-19 devnull i->li = IBF(w, 6, 29)<<2;
183 a84cbb2a 2004-04-19 devnull if(IB(w, 6))
184 310ae033 2017-01-06 rsc i->li |= ~0UL<<25;
185 a84cbb2a 2004-04-19 devnull i->lk = IB(w, 31);
186 a84cbb2a 2004-04-19 devnull i->mb = IBF(w, 21, 25);
187 a84cbb2a 2004-04-19 devnull i->me = IBF(w, 26, 30);
188 a84cbb2a 2004-04-19 devnull i->nb = IBF(w, 16, 20);
189 a84cbb2a 2004-04-19 devnull i->op = IBF(w, 0, 5);
190 a84cbb2a 2004-04-19 devnull i->oe = IB(w, 21);
191 a84cbb2a 2004-04-19 devnull i->ra = IBF(w, 11, 15);
192 a84cbb2a 2004-04-19 devnull i->rb = IBF(w, 16, 20);
193 a84cbb2a 2004-04-19 devnull i->rc = IB(w, 31);
194 a84cbb2a 2004-04-19 devnull i->rs = IBF(w, 6, 10); /* also rd */
195 a84cbb2a 2004-04-19 devnull i->sh = IBF(w, 16, 20);
196 a84cbb2a 2004-04-19 devnull i->spr = IBF(w, 11, 20);
197 a84cbb2a 2004-04-19 devnull i->to = IBF(w, 6, 10);
198 a84cbb2a 2004-04-19 devnull i->imm = IBF(w, 16, 19);
199 a84cbb2a 2004-04-19 devnull i->xo = IBF(w, 21, 30); /* bits 21-30, 22-30, 26-30, or 30 (beware) */
200 a84cbb2a 2004-04-19 devnull i->immediate = i->simm;
201 a84cbb2a 2004-04-19 devnull if(i->op == 15)
202 a84cbb2a 2004-04-19 devnull i->immediate <<= 16;
203 a84cbb2a 2004-04-19 devnull i->w0 = w;
204 a84cbb2a 2004-04-19 devnull i->target = -1;
205 a84cbb2a 2004-04-19 devnull i->addr = pc;
206 a84cbb2a 2004-04-19 devnull i->size = 1;
207 a84cbb2a 2004-04-19 devnull return 1;
210 a84cbb2a 2004-04-19 devnull static int
211 a84cbb2a 2004-04-19 devnull mkinstr(ulong pc, Instr *i)
213 a84cbb2a 2004-04-19 devnull Instr x;
215 a84cbb2a 2004-04-19 devnull if(decode(pc, i) < 0)
216 a84cbb2a 2004-04-19 devnull return -1;
218 a84cbb2a 2004-04-19 devnull * combine ADDIS/ORI (CAU/ORIL) into MOVW
220 a84cbb2a 2004-04-19 devnull if (i->op == 15 && i->ra==0) {
221 a84cbb2a 2004-04-19 devnull if(decode(pc+4, &x) < 0)
222 a84cbb2a 2004-04-19 devnull return -1;
223 a84cbb2a 2004-04-19 devnull if (x.op == 24 && x.rs == x.ra && x.ra == i->rd) {
224 a84cbb2a 2004-04-19 devnull i->immediate |= (x.immediate & 0xFFFF);
225 a84cbb2a 2004-04-19 devnull i->w1 = x.w0;
226 a84cbb2a 2004-04-19 devnull i->target = x.rd;
227 a84cbb2a 2004-04-19 devnull i->size++;
228 a84cbb2a 2004-04-19 devnull return 1;
231 a84cbb2a 2004-04-19 devnull return 1;
234 a84cbb2a 2004-04-19 devnull static int
235 a84cbb2a 2004-04-19 devnull plocal(Instr *i)
237 a84cbb2a 2004-04-19 devnull Symbol s;
238 a84cbb2a 2004-04-19 devnull Loc l, li;
240 a84cbb2a 2004-04-19 devnull l.type = LOFFSET;
241 a84cbb2a 2004-04-19 devnull l.offset = i->immediate;
242 a84cbb2a 2004-04-19 devnull l.reg = "SP";
244 a84cbb2a 2004-04-19 devnull li.type = LADDR;
245 a84cbb2a 2004-04-19 devnull li.addr = i->addr;
246 a84cbb2a 2004-04-19 devnull if (findsym(li, CTEXT, &s)<0 || findlsym(&s, l, &s)<0)
247 a84cbb2a 2004-04-19 devnull return -1;
248 a84cbb2a 2004-04-19 devnull bprint(i, "%s%+ld(SP)", s.name, (long)i->immediate);
249 a84cbb2a 2004-04-19 devnull return 0;
252 a84cbb2a 2004-04-19 devnull static int
253 a84cbb2a 2004-04-19 devnull pglobal(Instr *i, long off, int anyoff, char *reg)
255 a84cbb2a 2004-04-19 devnull Symbol s, s2;
256 a84cbb2a 2004-04-19 devnull u32int off1;
259 a84cbb2a 2004-04-19 devnull l.type = LADDR;
260 a84cbb2a 2004-04-19 devnull l.addr = off;
261 a84cbb2a 2004-04-19 devnull if(findsym(l, CANY, &s)>=0 && s.loc.type==LADDR &&
262 a84cbb2a 2004-04-19 devnull s.loc.addr-off < 4096 &&
263 a84cbb2a 2004-04-19 devnull (s.class == CDATA || s.class == CTEXT)) {
264 a84cbb2a 2004-04-19 devnull if(off==s.loc.addr && s.name[0]=='$'){
265 a84cbb2a 2004-04-19 devnull off1 = 0;
266 a84cbb2a 2004-04-19 devnull get4(mymap, s.loc.addr, &off1);
267 a84cbb2a 2004-04-19 devnull l.addr = off1;
268 a84cbb2a 2004-04-19 devnull if(off1 && findsym(l, CANY, &s2)>=0 && s2.loc.type==LADDR && s2.loc.addr == off1){
269 a84cbb2a 2004-04-19 devnull bprint(i, "$%s%s", s2.name, reg);
270 a84cbb2a 2004-04-19 devnull return 1;
273 a84cbb2a 2004-04-19 devnull bprint(i, "%s", s.name);
274 a84cbb2a 2004-04-19 devnull if (s.loc.addr != off)
275 a84cbb2a 2004-04-19 devnull bprint(i, "+%lux", off-s.loc.addr);
276 a84cbb2a 2004-04-19 devnull bprint(i, reg);
277 a84cbb2a 2004-04-19 devnull return 1;
279 a84cbb2a 2004-04-19 devnull if(!anyoff)
280 a84cbb2a 2004-04-19 devnull return 0;
281 a84cbb2a 2004-04-19 devnull bprint(i, "%lux%s", off, reg);
282 a84cbb2a 2004-04-19 devnull return 1;
285 a84cbb2a 2004-04-19 devnull static void
286 a84cbb2a 2004-04-19 devnull address(Instr *i)
288 a84cbb2a 2004-04-19 devnull if (i->ra == REGSP && plocal(i) >= 0)
290 a84cbb2a 2004-04-19 devnull if (i->ra == REGSB && mach->sb && pglobal(i, mach->sb+i->immediate, 0, "(SB)") >= 0)
292 a84cbb2a 2004-04-19 devnull if(i->simm < 0)
293 a84cbb2a 2004-04-19 devnull bprint(i, "-%lx(R%d)", -i->simm, i->ra);
295 a84cbb2a 2004-04-19 devnull bprint(i, "%lux(R%d)", i->immediate, i->ra);
298 a84cbb2a 2004-04-19 devnull static char *tcrbits[] = {"LT", "GT", "EQ", "VS"};
299 a84cbb2a 2004-04-19 devnull static char *fcrbits[] = {"GE", "LE", "NE", "VC"};
301 a84cbb2a 2004-04-19 devnull typedef struct Opcode Opcode;
303 a84cbb2a 2004-04-19 devnull struct Opcode {
304 a84cbb2a 2004-04-19 devnull uchar op;
305 a84cbb2a 2004-04-19 devnull ushort xo;
306 a84cbb2a 2004-04-19 devnull ushort xomask;
307 a84cbb2a 2004-04-19 devnull char *mnemonic;
308 a84cbb2a 2004-04-19 devnull void (*f)(Opcode *, Instr *);
309 a84cbb2a 2004-04-19 devnull char *ken;
310 a84cbb2a 2004-04-19 devnull int flags;
313 a84cbb2a 2004-04-19 devnull static void format(char *, Instr *, char *);
315 a84cbb2a 2004-04-19 devnull static void
316 a84cbb2a 2004-04-19 devnull branch(Opcode *o, Instr *i)
318 a84cbb2a 2004-04-19 devnull char buf[8];
319 a84cbb2a 2004-04-19 devnull int bo, bi;
321 a84cbb2a 2004-04-19 devnull bo = i->bo & ~1; /* ignore prediction bit */
322 a84cbb2a 2004-04-19 devnull if(bo==4 || bo==12 || bo==20) { /* simple forms */
323 a84cbb2a 2004-04-19 devnull if(bo != 20) {
324 a84cbb2a 2004-04-19 devnull bi = i->bi&3;
325 a84cbb2a 2004-04-19 devnull sprint(buf, "B%s%%L", bo==12? tcrbits[bi]: fcrbits[bi]);
326 a84cbb2a 2004-04-19 devnull format(buf, i, 0);
327 a84cbb2a 2004-04-19 devnull bprint(i, "\t");
328 a84cbb2a 2004-04-19 devnull if(i->bi > 4)
329 a84cbb2a 2004-04-19 devnull bprint(i, "CR(%d),", i->bi/4);
331 a84cbb2a 2004-04-19 devnull format("BR%L\t", i, 0);
332 a84cbb2a 2004-04-19 devnull if(i->op == 16)
333 a84cbb2a 2004-04-19 devnull format(0, i, "%J");
334 a84cbb2a 2004-04-19 devnull else if(i->op == 19 && i->xo == 528)
335 a84cbb2a 2004-04-19 devnull format(0, i, "(CTR)");
336 a84cbb2a 2004-04-19 devnull else if(i->op == 19 && i->xo == 16)
337 a84cbb2a 2004-04-19 devnull format(0, i, "(LR)");
339 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
342 a84cbb2a 2004-04-19 devnull static void
343 a84cbb2a 2004-04-19 devnull addi(Opcode *o, Instr *i)
345 a84cbb2a 2004-04-19 devnull if (i->op==14 && i->ra == 0)
346 a84cbb2a 2004-04-19 devnull format("MOVW", i, "%i,R%d");
347 a84cbb2a 2004-04-19 devnull else if (i->ra == REGSB) {
348 a84cbb2a 2004-04-19 devnull bprint(i, "MOVW\t$");
349 a84cbb2a 2004-04-19 devnull address(i);
350 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
351 a84cbb2a 2004-04-19 devnull } else if(i->op==14 && i->simm < 0) {
352 a84cbb2a 2004-04-19 devnull bprint(i, "SUB\t$%d,R%d", -i->simm, i->ra);
353 a84cbb2a 2004-04-19 devnull if(i->rd != i->ra)
354 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
355 a84cbb2a 2004-04-19 devnull } else if(i->ra == i->rd) {
356 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "%i");
357 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
359 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
362 a84cbb2a 2004-04-19 devnull static void
363 a84cbb2a 2004-04-19 devnull addis(Opcode *o, Instr *i)
367 a84cbb2a 2004-04-19 devnull v = i->immediate;
368 a84cbb2a 2004-04-19 devnull if (i->op==15 && i->ra == 0)
369 a84cbb2a 2004-04-19 devnull bprint(i, "MOVW\t$%lux,R%d", v, i->rd);
370 a84cbb2a 2004-04-19 devnull else if (i->op==15 && i->ra == REGSB) {
371 a84cbb2a 2004-04-19 devnull bprint(i, "MOVW\t$");
372 a84cbb2a 2004-04-19 devnull address(i);
373 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
374 a84cbb2a 2004-04-19 devnull } else if(i->op==15 && v < 0) {
375 a84cbb2a 2004-04-19 devnull bprint(i, "SUB\t$%d,R%d", -v, i->ra);
376 a84cbb2a 2004-04-19 devnull if(i->rd != i->ra)
377 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
378 a84cbb2a 2004-04-19 devnull } else {
379 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, 0);
380 a84cbb2a 2004-04-19 devnull bprint(i, "\t$%ld,R%d", v, i->ra);
381 a84cbb2a 2004-04-19 devnull if(i->rd != i->ra)
382 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
386 a84cbb2a 2004-04-19 devnull static void
387 a84cbb2a 2004-04-19 devnull andi(Opcode *o, Instr *i)
389 a84cbb2a 2004-04-19 devnull if (i->ra == i->rs)
390 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "%I,R%d");
392 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
395 a84cbb2a 2004-04-19 devnull static void
396 a84cbb2a 2004-04-19 devnull gencc(Opcode *o, Instr *i)
398 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
401 a84cbb2a 2004-04-19 devnull static void
402 a84cbb2a 2004-04-19 devnull gen(Opcode *o, Instr *i)
404 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
405 a84cbb2a 2004-04-19 devnull if (i->rc)
406 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
409 a84cbb2a 2004-04-19 devnull static void
410 a84cbb2a 2004-04-19 devnull ldx(Opcode *o, Instr *i)
412 a84cbb2a 2004-04-19 devnull if(i->ra == 0)
413 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b),R%d");
415 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b+R%a),R%d");
416 a84cbb2a 2004-04-19 devnull if(i->rc)
417 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
420 a84cbb2a 2004-04-19 devnull static void
421 a84cbb2a 2004-04-19 devnull stx(Opcode *o, Instr *i)
423 a84cbb2a 2004-04-19 devnull if(i->ra == 0)
424 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%d,(R%b)");
426 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%d,(R%b+R%a)");
427 a84cbb2a 2004-04-19 devnull if(i->rc && i->xo != 150)
428 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
431 a84cbb2a 2004-04-19 devnull static void
432 a84cbb2a 2004-04-19 devnull fldx(Opcode *o, Instr *i)
434 a84cbb2a 2004-04-19 devnull if(i->ra == 0)
435 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b),F%d");
437 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b+R%a),F%d");
438 a84cbb2a 2004-04-19 devnull if(i->rc)
439 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
442 a84cbb2a 2004-04-19 devnull static void
443 a84cbb2a 2004-04-19 devnull fstx(Opcode *o, Instr *i)
445 a84cbb2a 2004-04-19 devnull if(i->ra == 0)
446 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "F%d,(R%b)");
448 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "F%d,(R%b+R%a)");
449 a84cbb2a 2004-04-19 devnull if(i->rc)
450 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
453 a84cbb2a 2004-04-19 devnull static void
454 a84cbb2a 2004-04-19 devnull dcb(Opcode *o, Instr *i)
456 a84cbb2a 2004-04-19 devnull if(i->ra == 0)
457 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b)");
459 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "(R%b+R%a)");
460 a84cbb2a 2004-04-19 devnull if(i->rd)
461 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rd]");
462 a84cbb2a 2004-04-19 devnull if(i->rc)
463 a84cbb2a 2004-04-19 devnull bprint(i, " [illegal Rc]");
466 a84cbb2a 2004-04-19 devnull static void
467 a84cbb2a 2004-04-19 devnull lw(Opcode *o, Instr *i, char r)
469 a84cbb2a 2004-04-19 devnull bprint(i, "%s\t", o->mnemonic);
470 a84cbb2a 2004-04-19 devnull address(i);
471 a84cbb2a 2004-04-19 devnull bprint(i, ",%c%d", r, i->rd);
474 a84cbb2a 2004-04-19 devnull static void
475 a84cbb2a 2004-04-19 devnull load(Opcode *o, Instr *i)
477 a84cbb2a 2004-04-19 devnull lw(o, i, 'R');
480 a84cbb2a 2004-04-19 devnull static void
481 a84cbb2a 2004-04-19 devnull fload(Opcode *o, Instr *i)
483 a84cbb2a 2004-04-19 devnull lw(o, i, 'F');
486 a84cbb2a 2004-04-19 devnull static void
487 a84cbb2a 2004-04-19 devnull sw(Opcode *o, Instr *i, char r)
489 a84cbb2a 2004-04-19 devnull char *m;
490 a84cbb2a 2004-04-19 devnull Symbol s;
493 a84cbb2a 2004-04-19 devnull m = o->mnemonic;
494 a84cbb2a 2004-04-19 devnull if (i->rs == REGSP) {
495 a84cbb2a 2004-04-19 devnull l.type = LADDR;
496 a84cbb2a 2004-04-19 devnull l.addr = i->addr;
497 a84cbb2a 2004-04-19 devnull if (findsym(l, CTEXT, &s)>=0) {
498 a84cbb2a 2004-04-19 devnull l.type = LOFFSET;
499 a84cbb2a 2004-04-19 devnull l.reg = "SP";
500 a84cbb2a 2004-04-19 devnull l.offset = i->immediate;
501 a84cbb2a 2004-04-19 devnull if (findlsym(&s, l, &s) >= 0) {
502 a84cbb2a 2004-04-19 devnull bprint(i, "%s\t%c%d,%s-%d(SP)", m, r, i->rd,
503 a84cbb2a 2004-04-19 devnull s.name, i->immediate);
508 a84cbb2a 2004-04-19 devnull if (i->rs == REGSB && mach->sb) {
509 a84cbb2a 2004-04-19 devnull bprint(i, "%s\t%c%d,", m, r, i->rd);
510 a84cbb2a 2004-04-19 devnull address(i);
513 a84cbb2a 2004-04-19 devnull if (r == 'F')
514 a84cbb2a 2004-04-19 devnull format(m, i, "F%d,%l");
516 a84cbb2a 2004-04-19 devnull format(m, i, o->ken);
519 a84cbb2a 2004-04-19 devnull static void
520 a84cbb2a 2004-04-19 devnull store(Opcode *o, Instr *i)
522 a84cbb2a 2004-04-19 devnull sw(o, i, 'R');
525 a84cbb2a 2004-04-19 devnull static void
526 a84cbb2a 2004-04-19 devnull fstore(Opcode *o, Instr *i)
528 a84cbb2a 2004-04-19 devnull sw(o, i, 'F');
531 a84cbb2a 2004-04-19 devnull static void
532 a84cbb2a 2004-04-19 devnull shifti(Opcode *o, Instr *i)
534 a84cbb2a 2004-04-19 devnull if (i->ra == i->rs)
535 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "$%k,R%a");
537 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
540 a84cbb2a 2004-04-19 devnull static void
541 a84cbb2a 2004-04-19 devnull shift(Opcode *o, Instr *i)
543 a84cbb2a 2004-04-19 devnull if (i->ra == i->rs)
544 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%b,R%a");
546 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
549 a84cbb2a 2004-04-19 devnull static void
550 a84cbb2a 2004-04-19 devnull add(Opcode *o, Instr *i)
552 a84cbb2a 2004-04-19 devnull if (i->rd == i->ra)
553 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%b,R%d");
554 a84cbb2a 2004-04-19 devnull else if (i->rd == i->rb)
555 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%a,R%d");
557 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
560 a84cbb2a 2004-04-19 devnull static void
561 a84cbb2a 2004-04-19 devnull sub(Opcode *o, Instr *i)
563 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, 0);
564 a84cbb2a 2004-04-19 devnull bprint(i, "\t");
565 a84cbb2a 2004-04-19 devnull if(i->op == 31) {
566 a84cbb2a 2004-04-19 devnull bprint(i, "\tR%d,R%d", i->ra, i->rb); /* subtract Ra from Rb */
567 a84cbb2a 2004-04-19 devnull if(i->rd != i->rb)
568 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
570 a84cbb2a 2004-04-19 devnull bprint(i, "\tR%d,$%d,R%d", i->ra, i->simm, i->rd);
573 b8f742db 2005-01-11 devnull #define div power_div
575 a84cbb2a 2004-04-19 devnull static void
576 a84cbb2a 2004-04-19 devnull div(Opcode *o, Instr *i)
578 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, 0);
579 a84cbb2a 2004-04-19 devnull if(i->op == 31)
580 a84cbb2a 2004-04-19 devnull bprint(i, "\tR%d,R%d", i->rb, i->ra);
582 a84cbb2a 2004-04-19 devnull bprint(i, "\t$%d,R%d", i->simm, i->ra);
583 a84cbb2a 2004-04-19 devnull if(i->ra != i->rd)
584 a84cbb2a 2004-04-19 devnull bprint(i, ",R%d", i->rd);
587 a84cbb2a 2004-04-19 devnull static void
588 a84cbb2a 2004-04-19 devnull and(Opcode *o, Instr *i)
590 a84cbb2a 2004-04-19 devnull if (i->op == 31) {
591 a84cbb2a 2004-04-19 devnull /* Rb,Rs,Ra */
592 a84cbb2a 2004-04-19 devnull if (i->ra == i->rs)
593 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%b,R%a");
594 a84cbb2a 2004-04-19 devnull else if (i->ra == i->rb)
595 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%s,R%a");
597 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
598 a84cbb2a 2004-04-19 devnull } else {
599 a84cbb2a 2004-04-19 devnull /* imm,Rs,Ra */
600 a84cbb2a 2004-04-19 devnull if (i->ra == i->rs)
601 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "%I,R%a");
603 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
607 a84cbb2a 2004-04-19 devnull static void
608 a84cbb2a 2004-04-19 devnull or(Opcode *o, Instr *i)
610 a84cbb2a 2004-04-19 devnull if (i->op == 31) {
611 a84cbb2a 2004-04-19 devnull /* Rb,Rs,Ra */
612 a84cbb2a 2004-04-19 devnull if (i->rs == 0 && i->ra == 0 && i->rb == 0)
613 a84cbb2a 2004-04-19 devnull format("NOP", i, 0);
614 a84cbb2a 2004-04-19 devnull else if (i->rs == i->rb)
615 a84cbb2a 2004-04-19 devnull format("MOVW", i, "R%b,R%a");
617 a84cbb2a 2004-04-19 devnull and(o, i);
619 a84cbb2a 2004-04-19 devnull and(o, i);
622 a84cbb2a 2004-04-19 devnull static void
623 a84cbb2a 2004-04-19 devnull shifted(Opcode *o, Instr *i)
625 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, 0);
626 a84cbb2a 2004-04-19 devnull bprint(i, "\t$%lux,", (ulong)i->uimm<<16);
627 a84cbb2a 2004-04-19 devnull if (i->rs == i->ra)
628 a84cbb2a 2004-04-19 devnull bprint(i, "R%d", i->ra);
630 a84cbb2a 2004-04-19 devnull bprint(i, "R%d,R%d", i->rs, i->ra);
633 a84cbb2a 2004-04-19 devnull static void
634 a84cbb2a 2004-04-19 devnull neg(Opcode *o, Instr *i)
636 a84cbb2a 2004-04-19 devnull if (i->rd == i->ra)
637 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, "R%d");
639 a84cbb2a 2004-04-19 devnull format(o->mnemonic, i, o->ken);
642 a84cbb2a 2004-04-19 devnull static char ir2[] = "R%a,R%d"; /* reverse of IBM order */
643 a84cbb2a 2004-04-19 devnull static char ir3[] = "R%b,R%a,R%d";
644 a84cbb2a 2004-04-19 devnull static char ir3r[] = "R%a,R%b,R%d";
645 a84cbb2a 2004-04-19 devnull static char il3[] = "R%b,R%s,R%a";
646 a84cbb2a 2004-04-19 devnull static char il2u[] = "%I,R%a,R%d";
647 a84cbb2a 2004-04-19 devnull static char il3s[] = "$%k,R%s,R%a";
648 a84cbb2a 2004-04-19 devnull static char il2[] = "R%s,R%a";
649 a84cbb2a 2004-04-19 devnull static char icmp3[] = "R%a,R%b,%D";
650 a84cbb2a 2004-04-19 devnull static char cr3op[] = "%b,%a,%d";
651 a84cbb2a 2004-04-19 devnull static char ir2i[] = "%i,R%a,R%d";
652 a84cbb2a 2004-04-19 devnull static char fp2[] = "F%b,F%d";
653 a84cbb2a 2004-04-19 devnull static char fp3[] = "F%b,F%a,F%d";
654 a84cbb2a 2004-04-19 devnull static char fp3c[] = "F%c,F%a,F%d";
655 a84cbb2a 2004-04-19 devnull static char fp4[] = "F%a,F%c,F%b,F%d";
656 a84cbb2a 2004-04-19 devnull static char fpcmp[] = "F%a,F%b,%D";
657 a84cbb2a 2004-04-19 devnull static char ldop[] = "%l,R%d";
658 a84cbb2a 2004-04-19 devnull static char stop[] = "R%d,%l";
659 a84cbb2a 2004-04-19 devnull static char fldop[] = "%l,F%d";
660 a84cbb2a 2004-04-19 devnull static char fstop[] = "F%d,%l";
661 a84cbb2a 2004-04-19 devnull static char rlim[] = "R%b,R%s,$%z,R%a";
662 a84cbb2a 2004-04-19 devnull static char rlimi[] = "$%k,R%s,$%z,R%a";
664 a84cbb2a 2004-04-19 devnull #define OEM IBF(~0,22,30)
665 a84cbb2a 2004-04-19 devnull #define FP4 IBF(~0,26,30)
666 a0f1e21f 2004-04-20 devnull #define ALL ((ushort)~0)
669 a84cbb2a 2004-04-19 devnull 10-26: crfD = rD>>2; rD&3 mbz
670 a84cbb2a 2004-04-19 devnull also, L bit (bit 10) mbz or selects 64-bit operands
673 a84cbb2a 2004-04-19 devnull static Opcode opcodes[] = {
674 a84cbb2a 2004-04-19 devnull {31, 360, OEM, "ABS%V%C", 0, ir2}, /* POWER */
676 a84cbb2a 2004-04-19 devnull {31, 266, OEM, "ADD%V%C", add, ir3},
677 a84cbb2a 2004-04-19 devnull {31, 10, OEM, "ADDC%V%C", add, ir3},
678 a84cbb2a 2004-04-19 devnull {31, 138, OEM, "ADDE%V%C", add, ir3},
679 a84cbb2a 2004-04-19 devnull {14, 0, 0, "ADD", addi, ir2i},
680 a84cbb2a 2004-04-19 devnull {12, 0, 0, "ADDC", addi, ir2i},
681 a84cbb2a 2004-04-19 devnull {13, 0, 0, "ADDCCC", addi, ir2i},
682 a84cbb2a 2004-04-19 devnull {15, 0, 0, "ADD", addis, 0},
683 a84cbb2a 2004-04-19 devnull {31, 234, OEM, "ADDME%V%C", gencc, ir2},
684 a84cbb2a 2004-04-19 devnull {31, 202, OEM, "ADDZE%V%C", gencc, ir2},
686 a84cbb2a 2004-04-19 devnull {31, 28, ALL, "AND%C", and, il3},
687 a84cbb2a 2004-04-19 devnull {31, 60, ALL, "ANDN%C", and, il3},
688 a84cbb2a 2004-04-19 devnull {28, 0, 0, "ANDCC", andi, il2u},
689 a84cbb2a 2004-04-19 devnull {29, 0, 0, "ANDCC", shifted, 0},
691 a84cbb2a 2004-04-19 devnull {18, 0, 0, "B%L", gencc, "%j"},
692 a84cbb2a 2004-04-19 devnull {16, 0, 0, "BC%L", branch, "%d,%a,%J"},
693 a84cbb2a 2004-04-19 devnull {19, 528, ALL, "BC%L", branch, "%d,%a,(CTR)"},
694 a84cbb2a 2004-04-19 devnull {19, 16, ALL, "BC%L", branch, "%d,%a,(LR)"},
696 a84cbb2a 2004-04-19 devnull {31, 531, ALL, "CLCS", gen, ir2}, /* POWER */
698 a84cbb2a 2004-04-19 devnull {31, 0, ALL, "CMP", 0, icmp3},
699 a84cbb2a 2004-04-19 devnull {11, 0, 0, "CMP", 0, "R%a,%i,%D"},
700 a84cbb2a 2004-04-19 devnull {31, 32, ALL, "CMPU", 0, icmp3},
701 a84cbb2a 2004-04-19 devnull {10, 0, 0, "CMPU", 0, "R%a,%I,%D"},
703 a84cbb2a 2004-04-19 devnull {31, 26, ALL, "CNTLZ%C", gencc, ir2},
705 a84cbb2a 2004-04-19 devnull {19, 257, ALL, "CRAND", gen, cr3op},
706 a84cbb2a 2004-04-19 devnull {19, 129, ALL, "CRANDN", gen, cr3op},
707 a84cbb2a 2004-04-19 devnull {19, 289, ALL, "CREQV", gen, cr3op},
708 a84cbb2a 2004-04-19 devnull {19, 225, ALL, "CRNAND", gen, cr3op},
709 a84cbb2a 2004-04-19 devnull {19, 33, ALL, "CRNOR", gen, cr3op},
710 a84cbb2a 2004-04-19 devnull {19, 449, ALL, "CROR", gen, cr3op},
711 a84cbb2a 2004-04-19 devnull {19, 417, ALL, "CRORN", gen, cr3op},
712 a84cbb2a 2004-04-19 devnull {19, 193, ALL, "CRXOR", gen, cr3op},
714 a84cbb2a 2004-04-19 devnull {31, 86, ALL, "DCBF", dcb, 0},
715 a84cbb2a 2004-04-19 devnull {31, 470, ALL, "DCBI", dcb, 0},
716 a84cbb2a 2004-04-19 devnull {31, 54, ALL, "DCBST", dcb, 0},
717 a84cbb2a 2004-04-19 devnull {31, 278, ALL, "DCBT", dcb, 0},
718 a84cbb2a 2004-04-19 devnull {31, 246, ALL, "DCBTST", dcb, 0},
719 a84cbb2a 2004-04-19 devnull {31, 1014, ALL, "DCBZ", dcb, 0},
721 a84cbb2a 2004-04-19 devnull {31, 331, OEM, "DIV%V%C", div, ir3}, /* POWER */
722 a84cbb2a 2004-04-19 devnull {31, 363, OEM, "DIVS%V%C", div, ir3}, /* POWER */
723 a84cbb2a 2004-04-19 devnull {31, 491, OEM, "DIVW%V%C", div, ir3},
724 a84cbb2a 2004-04-19 devnull {31, 459, OEM, "DIVWU%V%C", div, ir3},
726 a84cbb2a 2004-04-19 devnull {31, 264, OEM, "DOZ%V%C", gencc, ir3r}, /* POWER */
727 a84cbb2a 2004-04-19 devnull {9, 0, 0, "DOZ", gen, ir2i}, /* POWER */
729 a84cbb2a 2004-04-19 devnull {31, 310, ALL, "ECIWX", ldx, 0},
730 a84cbb2a 2004-04-19 devnull {31, 438, ALL, "ECOWX", stx, 0},
731 a84cbb2a 2004-04-19 devnull {31, 854, ALL, "EIEIO", gen, 0},
733 a84cbb2a 2004-04-19 devnull {31, 284, ALL, "EQV%C", gencc, il3},
735 a84cbb2a 2004-04-19 devnull {31, 954, ALL, "EXTSB%C", gencc, il2},
736 a84cbb2a 2004-04-19 devnull {31, 922, ALL, "EXTSH%C", gencc, il2},
738 a84cbb2a 2004-04-19 devnull {63, 264, ALL, "FABS%C", gencc, fp2},
739 a84cbb2a 2004-04-19 devnull {63, 21, ALL, "FADD%C", gencc, fp3},
740 a84cbb2a 2004-04-19 devnull {59, 21, ALL, "FADDS%C", gencc, fp3},
741 a84cbb2a 2004-04-19 devnull {63, 32, ALL, "FCMPO", gen, fpcmp},
742 a84cbb2a 2004-04-19 devnull {63, 0, ALL, "FCMPU", gen, fpcmp},
743 a84cbb2a 2004-04-19 devnull {63, 14, ALL, "FCTIW%C", gencc, fp2},
744 a84cbb2a 2004-04-19 devnull {63, 15, ALL, "FCTIWZ%C", gencc, fp2},
745 a84cbb2a 2004-04-19 devnull {63, 18, ALL, "FDIV%C", gencc, fp3},
746 a84cbb2a 2004-04-19 devnull {59, 18, ALL, "FDIVS%C", gencc, fp3},
747 a84cbb2a 2004-04-19 devnull {63, 29, FP4, "FMADD%C", gencc, fp4},
748 a84cbb2a 2004-04-19 devnull {59, 29, FP4, "FMADDS%C", gencc, fp4},
749 a84cbb2a 2004-04-19 devnull {63, 72, ALL, "FMOVD%C", gencc, fp2},
750 a84cbb2a 2004-04-19 devnull {63, 28, FP4, "FMSUB%C", gencc, fp4},
751 a84cbb2a 2004-04-19 devnull {59, 28, FP4, "FMSUBS%C", gencc, fp4},
752 a84cbb2a 2004-04-19 devnull {63, 25, FP4, "FMUL%C", gencc, fp3c},
753 a84cbb2a 2004-04-19 devnull {59, 25, FP4, "FMULS%C", gencc, fp3c},
754 a84cbb2a 2004-04-19 devnull {63, 136, ALL, "FNABS%C", gencc, fp2},
755 a84cbb2a 2004-04-19 devnull {63, 40, ALL, "FNEG%C", gencc, fp2},
756 a84cbb2a 2004-04-19 devnull {63, 31, FP4, "FNMADD%C", gencc, fp4},
757 a84cbb2a 2004-04-19 devnull {59, 31, FP4, "FNMADDS%C", gencc, fp4},
758 a84cbb2a 2004-04-19 devnull {63, 30, FP4, "FNMSUB%C", gencc, fp4},
759 a84cbb2a 2004-04-19 devnull {59, 30, FP4, "FNMSUBS%C", gencc, fp4},
760 a84cbb2a 2004-04-19 devnull {63, 12, ALL, "FRSP%C", gencc, fp2},
761 a84cbb2a 2004-04-19 devnull {63, 20, FP4, "FSUB%C", gencc, fp3},
762 a84cbb2a 2004-04-19 devnull {59, 20, FP4, "FSUBS%C", gencc, fp3},
764 a84cbb2a 2004-04-19 devnull {31, 982, ALL, "ICBI", dcb, 0},
765 a84cbb2a 2004-04-19 devnull {19, 150, ALL, "ISYNC", gen, 0},
767 a84cbb2a 2004-04-19 devnull {34, 0, 0, "MOVBZ", load, ldop},
768 a84cbb2a 2004-04-19 devnull {35, 0, 0, "MOVBZU", load, ldop},
769 a84cbb2a 2004-04-19 devnull {31, 119, ALL, "MOVBZU", ldx, 0},
770 a84cbb2a 2004-04-19 devnull {31, 87, ALL, "MOVBZ", ldx, 0},
771 a84cbb2a 2004-04-19 devnull {50, 0, 0, "FMOVD", fload, fldop},
772 a84cbb2a 2004-04-19 devnull {51, 0, 0, "FMOVDU", fload, fldop},
773 a84cbb2a 2004-04-19 devnull {31, 631, ALL, "FMOVDU", fldx, 0},
774 a84cbb2a 2004-04-19 devnull {31, 599, ALL, "FMOVD", fldx, 0},
775 a84cbb2a 2004-04-19 devnull {48, 0, 0, "FMOVS", load, fldop},
776 a84cbb2a 2004-04-19 devnull {49, 0, 0, "FMOVSU", load, fldop},
777 a84cbb2a 2004-04-19 devnull {31, 567, ALL, "FMOVSU", fldx, 0},
778 a84cbb2a 2004-04-19 devnull {31, 535, ALL, "FMOVS", fldx, 0},
779 a84cbb2a 2004-04-19 devnull {42, 0, 0, "MOVH", load, ldop},
780 a84cbb2a 2004-04-19 devnull {43, 0, 0, "MOVHU", load, ldop},
781 a84cbb2a 2004-04-19 devnull {31, 375, ALL, "MOVHU", ldx, 0},
782 a84cbb2a 2004-04-19 devnull {31, 343, ALL, "MOVH", ldx, 0},
783 a84cbb2a 2004-04-19 devnull {31, 790, ALL, "MOVHBR", ldx, 0},
784 a84cbb2a 2004-04-19 devnull {40, 0, 0, "MOVHZ", load, ldop},
785 a84cbb2a 2004-04-19 devnull {41, 0, 0, "MOVHZU", load, ldop},
786 a84cbb2a 2004-04-19 devnull {31, 311, ALL, "MOVHZU", ldx, 0},
787 a84cbb2a 2004-04-19 devnull {31, 279, ALL, "MOVHZ", ldx, 0},
788 a84cbb2a 2004-04-19 devnull {46, 0, 0, "MOVMW", load, ldop},
789 a84cbb2a 2004-04-19 devnull {31, 277, ALL, "LSCBX%C", ldx, 0}, /* POWER */
790 a84cbb2a 2004-04-19 devnull {31, 597, ALL, "LSW", gen, "(R%a),$%n,R%d"},
791 a84cbb2a 2004-04-19 devnull {31, 533, ALL, "LSW", ldx, 0},
792 a84cbb2a 2004-04-19 devnull {31, 20, ALL, "LWAR", ldx, 0},
793 a84cbb2a 2004-04-19 devnull {31, 534, ALL, "MOVWBR", ldx, 0},
794 a84cbb2a 2004-04-19 devnull {32, 0, 0, "MOVW", load, ldop},
795 a84cbb2a 2004-04-19 devnull {33, 0, 0, "MOVWU", load, ldop},
796 a84cbb2a 2004-04-19 devnull {31, 55, ALL, "MOVWU", ldx, 0},
797 a84cbb2a 2004-04-19 devnull {31, 23, ALL, "MOVW", ldx, 0},
799 a84cbb2a 2004-04-19 devnull {31, 29, ALL, "MASKG%C", gencc, "R%s:R%b,R%d"}, /* POWER */
800 a84cbb2a 2004-04-19 devnull {31, 541, ALL, "MASKIR%C", gencc, "R%s,R%b,R%a"}, /* POWER */
802 a84cbb2a 2004-04-19 devnull {19, 0, ALL, "MOVFL", gen, "%S,%D"},
803 a84cbb2a 2004-04-19 devnull {63, 64, ALL, "MOVCRFS", gen, "%S,%D"},
804 a84cbb2a 2004-04-19 devnull {31, 512, ALL, "MOVW", gen, "XER,%D"},
805 a84cbb2a 2004-04-19 devnull {31, 19, ALL, "MOVW", gen, "CR,R%d"},
807 a84cbb2a 2004-04-19 devnull {63, 583, ALL, "MOVW%C", gen, "FPSCR, F%d"}, /* mffs */
808 a84cbb2a 2004-04-19 devnull {31, 83, ALL, "MOVW", gen, "MSR,R%d"},
809 a84cbb2a 2004-04-19 devnull {31, 339, ALL, "MOVW", gen, "%P,R%d"},
810 a84cbb2a 2004-04-19 devnull {31, 595, ALL, "MOVW", gen, "SEG(%a),R%d"},
811 a84cbb2a 2004-04-19 devnull {31, 659, ALL, "MOVW", gen, "SEG(R%b),R%d"},
812 a84cbb2a 2004-04-19 devnull {31, 144, ALL, "MOVFL", gen, "R%s,%m,CR"},
813 a84cbb2a 2004-04-19 devnull {63, 70, ALL, "MTFSB0%C", gencc, "%D"},
814 a84cbb2a 2004-04-19 devnull {63, 38, ALL, "MTFSB1%C", gencc, "%D"},
815 a84cbb2a 2004-04-19 devnull {63, 711, ALL, "MOVFL%C", gencc, "F%b,%M,FPSCR"}, /* mtfsf */
816 a84cbb2a 2004-04-19 devnull {63, 134, ALL, "MOVFL%C", gencc, "%K,%D"},
817 a84cbb2a 2004-04-19 devnull {31, 146, ALL, "MOVW", gen, "R%s,MSR"},
818 a84cbb2a 2004-04-19 devnull {31, 467, ALL, "MOVW", gen, "R%s,%P"},
819 a84cbb2a 2004-04-19 devnull {31, 210, ALL, "MOVW", gen, "R%s,SEG(%a)"},
820 a84cbb2a 2004-04-19 devnull {31, 242, ALL, "MOVW", gen, "R%s,SEG(R%b)"},
822 a84cbb2a 2004-04-19 devnull {31, 107, OEM, "MUL%V%C", gencc, ir3}, /* POWER */
823 a84cbb2a 2004-04-19 devnull {31, 75, ALL, "MULHW%C", gencc, ir3}, /* POWER */
824 a84cbb2a 2004-04-19 devnull {31, 11, ALL, "MULHWU%C", gencc, ir3}, /* POWER */
826 a84cbb2a 2004-04-19 devnull {31, 235, OEM, "MULLW%V%C", gencc, ir3},
827 a84cbb2a 2004-04-19 devnull {7, 0, 0, "MULLW", div, "%i,R%a,R%d"},
829 a84cbb2a 2004-04-19 devnull {31, 488, OEM, "NABS%V%C", neg, ir2}, /* POWER */
831 a84cbb2a 2004-04-19 devnull {31, 476, ALL, "NAND%C", gencc, il3},
832 a84cbb2a 2004-04-19 devnull {31, 104, OEM, "NEG%V%C", neg, ir2},
833 a84cbb2a 2004-04-19 devnull {31, 124, ALL, "NOR%C", gencc, il3},
834 a84cbb2a 2004-04-19 devnull {31, 444, ALL, "OR%C", or, il3},
835 a84cbb2a 2004-04-19 devnull {31, 412, ALL, "ORN%C", or, il3},
836 a84cbb2a 2004-04-19 devnull {24, 0, 0, "OR", and, "%I,R%d,R%a"},
837 a84cbb2a 2004-04-19 devnull {25, 0, 0, "OR", shifted, 0},
839 a84cbb2a 2004-04-19 devnull {19, 50, ALL, "RFI", gen, 0},
841 a84cbb2a 2004-04-19 devnull {22, 0, 0, "RLMI%C", gencc, rlim}, /* POWER */
842 a84cbb2a 2004-04-19 devnull {20, 0, 0, "RLWMI%C", gencc, rlimi},
843 a84cbb2a 2004-04-19 devnull {21, 0, 0, "RLWNM%C", gencc, rlimi},
844 a84cbb2a 2004-04-19 devnull {23, 0, 0, "RLWNM%C", gencc, rlim},
846 a84cbb2a 2004-04-19 devnull {31, 537, ALL, "RRIB%C", gencc, il3}, /* POWER */
848 a84cbb2a 2004-04-19 devnull {17, 1, ALL, "SYSCALL", gen, 0},
850 a84cbb2a 2004-04-19 devnull {31, 153, ALL, "SLE%C", shift, il3}, /* POWER */
851 a84cbb2a 2004-04-19 devnull {31, 217, ALL, "SLEQ%C", shift, il3}, /* POWER */
852 a84cbb2a 2004-04-19 devnull {31, 184, ALL, "SLQ%C", shifti, il3s}, /* POWER */
853 a84cbb2a 2004-04-19 devnull {31, 248, ALL, "SLLQ%C", shifti, il3s}, /* POWER */
854 a84cbb2a 2004-04-19 devnull {31, 216, ALL, "SLLQ%C", shift, il3}, /* POWER */
855 a84cbb2a 2004-04-19 devnull {31, 152, ALL, "SLQ%C", shift, il3}, /* POWER */
857 a84cbb2a 2004-04-19 devnull {31, 24, ALL, "SLW%C", shift, il3},
859 a84cbb2a 2004-04-19 devnull {31, 920, ALL, "SRAQ%C", shift, il3}, /* POWER */
860 a84cbb2a 2004-04-19 devnull {31, 952, ALL, "SRAQ%C", shifti, il3s}, /* POWER */
862 a84cbb2a 2004-04-19 devnull {31, 792, ALL, "SRAW%C", shift, il3},
863 a84cbb2a 2004-04-19 devnull {31, 824, ALL, "SRAW%C", shifti, il3s},
865 a84cbb2a 2004-04-19 devnull {31, 665, ALL, "SRE%C", shift, il3}, /* POWER */
866 a84cbb2a 2004-04-19 devnull {31, 921, ALL, "SREA%C", shift, il3}, /* POWER */
867 a84cbb2a 2004-04-19 devnull {31, 729, ALL, "SREQ%C", shift, il3}, /* POWER */
868 a84cbb2a 2004-04-19 devnull {31, 696, ALL, "SRQ%C", shifti, il3s}, /* POWER */
869 a84cbb2a 2004-04-19 devnull {31, 760, ALL, "SRLQ%C", shifti, il3s}, /* POWER */
870 a84cbb2a 2004-04-19 devnull {31, 728, ALL, "SRLQ%C", shift, il3}, /* POWER */
871 a84cbb2a 2004-04-19 devnull {31, 664, ALL, "SRQ%C", shift, il3}, /* POWER */
873 a84cbb2a 2004-04-19 devnull {31, 536, ALL, "SRW%C", shift, il3},
875 a84cbb2a 2004-04-19 devnull {38, 0, 0, "MOVB", store, stop},
876 a84cbb2a 2004-04-19 devnull {39, 0, 0, "MOVBU", store, stop},
877 a84cbb2a 2004-04-19 devnull {31, 247, ALL, "MOVBU", stx, 0},
878 a84cbb2a 2004-04-19 devnull {31, 215, ALL, "MOVB", stx, 0},
879 a84cbb2a 2004-04-19 devnull {54, 0, 0, "FMOVD", fstore, fstop},
880 a84cbb2a 2004-04-19 devnull {55, 0, 0, "FMOVDU", fstore, fstop},
881 a84cbb2a 2004-04-19 devnull {31, 759, ALL, "FMOVDU", fstx, 0},
882 a84cbb2a 2004-04-19 devnull {31, 727, ALL, "FMOVD", fstx, 0},
883 a84cbb2a 2004-04-19 devnull {52, 0, 0, "FMOVS", fstore, fstop},
884 a84cbb2a 2004-04-19 devnull {53, 0, 0, "FMOVSU", fstore, fstop},
885 a84cbb2a 2004-04-19 devnull {31, 695, ALL, "FMOVSU", fstx, 0},
886 a84cbb2a 2004-04-19 devnull {31, 663, ALL, "FMOVS", fstx, 0},
887 a84cbb2a 2004-04-19 devnull {44, 0, 0, "MOVH", store, stop},
888 a84cbb2a 2004-04-19 devnull {31, 918, ALL, "MOVHBR", stx, 0},
889 a84cbb2a 2004-04-19 devnull {45, 0, 0, "MOVHU", store, stop},
890 a84cbb2a 2004-04-19 devnull {31, 439, ALL, "MOVHU", stx, 0},
891 a84cbb2a 2004-04-19 devnull {31, 407, ALL, "MOVH", stx, 0},
892 a84cbb2a 2004-04-19 devnull {47, 0, 0, "MOVMW", store, stop},
893 a84cbb2a 2004-04-19 devnull {31, 725, ALL, "STSW", gen, "R%d,$%n,(R%a)"},
894 a84cbb2a 2004-04-19 devnull {31, 661, ALL, "STSW", stx, 0},
895 a84cbb2a 2004-04-19 devnull {36, 0, 0, "MOVW", store, stop},
896 a84cbb2a 2004-04-19 devnull {31, 662, ALL, "MOVWBR", stx, 0},
897 a84cbb2a 2004-04-19 devnull {31, 150, ALL, "STWCCC", stx, 0},
898 a84cbb2a 2004-04-19 devnull {37, 0, 0, "MOVWU", store, stop},
899 a84cbb2a 2004-04-19 devnull {31, 183, ALL, "MOVWU", stx, 0},
900 a84cbb2a 2004-04-19 devnull {31, 151, ALL, "MOVW", stx, 0},
902 a84cbb2a 2004-04-19 devnull {31, 40, OEM, "SUB%V%C", sub, ir3},
903 a84cbb2a 2004-04-19 devnull {31, 8, OEM, "SUBC%V%C", sub, ir3},
904 a84cbb2a 2004-04-19 devnull {31, 136, OEM, "SUBE%V%C", sub, ir3},
905 a84cbb2a 2004-04-19 devnull {8, 0, 0, "SUBC", gen, "R%a,%i,R%d"},
906 a84cbb2a 2004-04-19 devnull {31, 232, OEM, "SUBME%V%C", sub, ir2},
907 a84cbb2a 2004-04-19 devnull {31, 200, OEM, "SUBZE%V%C", sub, ir2},
909 a84cbb2a 2004-04-19 devnull {31, 598, ALL, "SYNC", gen, 0},
910 a84cbb2a 2004-04-19 devnull {31, 370, ALL, "TLBIA", gen, 0},
911 a84cbb2a 2004-04-19 devnull {31, 306, ALL, "TLBIE", gen, "R%b"},
912 a84cbb2a 2004-04-19 devnull {31, 1010, ALL, "TLBLI", gen, "R%b"},
913 a84cbb2a 2004-04-19 devnull {31, 978, ALL, "TLBLD", gen, "R%b"},
914 a84cbb2a 2004-04-19 devnull {31, 4, ALL, "TW", gen, "%d,R%a,R%b"},
915 a84cbb2a 2004-04-19 devnull {3, 0, 0, "TW", gen, "%d,R%a,%i"},
917 a84cbb2a 2004-04-19 devnull {31, 316, ALL, "XOR", and, il3},
918 a84cbb2a 2004-04-19 devnull {26, 0, 0, "XOR", and, il2u},
919 a84cbb2a 2004-04-19 devnull {27, 0, 0, "XOR", shifted, 0},
924 a84cbb2a 2004-04-19 devnull typedef struct Spr Spr;
925 a84cbb2a 2004-04-19 devnull struct Spr {
927 a84cbb2a 2004-04-19 devnull char *name;
930 a84cbb2a 2004-04-19 devnull static Spr sprname[] = {
931 a84cbb2a 2004-04-19 devnull {0, "MQ"},
932 a84cbb2a 2004-04-19 devnull {1, "XER"},
933 a84cbb2a 2004-04-19 devnull {268, "TBL"},
934 a84cbb2a 2004-04-19 devnull {269, "TBU"},
935 a84cbb2a 2004-04-19 devnull {8, "LR"},
936 a84cbb2a 2004-04-19 devnull {9, "CTR"},
937 a84cbb2a 2004-04-19 devnull {528, "IBAT0U"},
938 a84cbb2a 2004-04-19 devnull {529, "IBAT0L"},
939 a84cbb2a 2004-04-19 devnull {530, "IBAT1U"},
940 a84cbb2a 2004-04-19 devnull {531, "IBAT1L"},
941 a84cbb2a 2004-04-19 devnull {532, "IBAT2U"},
942 a84cbb2a 2004-04-19 devnull {533, "IBAT2L"},
943 a84cbb2a 2004-04-19 devnull {534, "IBAT3U"},
944 a84cbb2a 2004-04-19 devnull {535, "IBAT3L"},
945 a84cbb2a 2004-04-19 devnull {536, "DBAT0U"},
946 a84cbb2a 2004-04-19 devnull {537, "DBAT0L"},
947 a84cbb2a 2004-04-19 devnull {538, "DBAT1U"},
948 a84cbb2a 2004-04-19 devnull {539, "DBAT1L"},
949 a84cbb2a 2004-04-19 devnull {540, "DBAT2U"},
950 a84cbb2a 2004-04-19 devnull {541, "DBAT2L"},
951 a84cbb2a 2004-04-19 devnull {542, "DBAT3U"},
952 a84cbb2a 2004-04-19 devnull {543, "DBAT3L"},
953 a84cbb2a 2004-04-19 devnull {25, "SDR1"},
954 a84cbb2a 2004-04-19 devnull {19, "DAR"},
955 a84cbb2a 2004-04-19 devnull {272, "SPRG0"},
956 a84cbb2a 2004-04-19 devnull {273, "SPRG1"},
957 a84cbb2a 2004-04-19 devnull {274, "SPRG2"},
958 a84cbb2a 2004-04-19 devnull {275, "SPRG3"},
959 a84cbb2a 2004-04-19 devnull {18, "DSISR"},
960 a84cbb2a 2004-04-19 devnull {26, "SRR0"},
961 a84cbb2a 2004-04-19 devnull {27, "SRR1"},
962 a84cbb2a 2004-04-19 devnull {284, "TBLW"},
963 fa325e9b 2020-01-10 cross {285, "TBUW"},
964 a84cbb2a 2004-04-19 devnull {22, "DEC"},
965 a84cbb2a 2004-04-19 devnull {282, "EAR"},
966 a84cbb2a 2004-04-19 devnull {1008, "HID0"},
967 a84cbb2a 2004-04-19 devnull {1009, "HID1"},
968 a84cbb2a 2004-04-19 devnull {976, "DMISS"},
969 a84cbb2a 2004-04-19 devnull {977, "DCMP"},
970 a84cbb2a 2004-04-19 devnull {978, "HASH1"},
971 a84cbb2a 2004-04-19 devnull {979, "HASH2"},
972 a84cbb2a 2004-04-19 devnull {980, "IMISS"},
973 a84cbb2a 2004-04-19 devnull {981, "ICMP"},
974 a84cbb2a 2004-04-19 devnull {982, "RPA"},
975 a84cbb2a 2004-04-19 devnull {1010, "IABR"},
979 a84cbb2a 2004-04-19 devnull static void
980 a84cbb2a 2004-04-19 devnull format(char *mnemonic, Instr *i, char *f)
982 a84cbb2a 2004-04-19 devnull int n, s;
983 a84cbb2a 2004-04-19 devnull ulong mask;
985 a84cbb2a 2004-04-19 devnull if (mnemonic)
986 a84cbb2a 2004-04-19 devnull format(0, i, mnemonic);
987 a84cbb2a 2004-04-19 devnull if (f == 0)
989 a84cbb2a 2004-04-19 devnull if (mnemonic)
990 a84cbb2a 2004-04-19 devnull bprint(i, "\t");
991 a84cbb2a 2004-04-19 devnull for ( ; *f; f++) {
992 a84cbb2a 2004-04-19 devnull if (*f != '%') {
993 a84cbb2a 2004-04-19 devnull bprint(i, "%c", *f);
994 a84cbb2a 2004-04-19 devnull continue;
996 a84cbb2a 2004-04-19 devnull switch (*++f) {
997 a84cbb2a 2004-04-19 devnull case 'V':
998 a84cbb2a 2004-04-19 devnull if(i->oe)
999 a84cbb2a 2004-04-19 devnull bprint(i, "V");
1002 a84cbb2a 2004-04-19 devnull case 'C':
1003 a84cbb2a 2004-04-19 devnull if(i->rc)
1004 a84cbb2a 2004-04-19 devnull bprint(i, "CC");
1007 a84cbb2a 2004-04-19 devnull case 'a':
1008 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->ra);
1011 a84cbb2a 2004-04-19 devnull case 'b':
1012 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->rb);
1015 a84cbb2a 2004-04-19 devnull case 'c':
1016 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->frc);
1019 a84cbb2a 2004-04-19 devnull case 'd':
1020 a84cbb2a 2004-04-19 devnull case 's':
1021 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->rd);
1024 a84cbb2a 2004-04-19 devnull case 'S':
1025 a84cbb2a 2004-04-19 devnull if(i->ra & 3)
1026 a84cbb2a 2004-04-19 devnull bprint(i, "CR(INVAL:%d)", i->ra);
1027 a84cbb2a 2004-04-19 devnull else if(i->op == 63)
1028 a84cbb2a 2004-04-19 devnull bprint(i, "FPSCR(%d)", i->crfs);
1030 a84cbb2a 2004-04-19 devnull bprint(i, "CR(%d)", i->crfs);
1033 a84cbb2a 2004-04-19 devnull case 'D':
1034 a84cbb2a 2004-04-19 devnull if(i->rd & 3)
1035 a84cbb2a 2004-04-19 devnull bprint(i, "CR(INVAL:%d)", i->rd);
1036 a84cbb2a 2004-04-19 devnull else if(i->op == 63)
1037 a84cbb2a 2004-04-19 devnull bprint(i, "FPSCR(%d)", i->crfd);
1039 a84cbb2a 2004-04-19 devnull bprint(i, "CR(%d)", i->crfd);
1042 a84cbb2a 2004-04-19 devnull case 'l':
1043 a84cbb2a 2004-04-19 devnull if(i->simm < 0)
1044 a84cbb2a 2004-04-19 devnull bprint(i, "-%lx(R%d)", -i->simm, i->ra);
1046 a84cbb2a 2004-04-19 devnull bprint(i, "%lx(R%d)", i->simm, i->ra);
1049 a84cbb2a 2004-04-19 devnull case 'i':
1050 a84cbb2a 2004-04-19 devnull bprint(i, "$%ld", i->simm);
1053 a84cbb2a 2004-04-19 devnull case 'I':
1054 a84cbb2a 2004-04-19 devnull bprint(i, "$%lx", i->uimm);
1057 a84cbb2a 2004-04-19 devnull case 'w':
1058 a84cbb2a 2004-04-19 devnull bprint(i, "[%lux]", i->w0);
1061 a84cbb2a 2004-04-19 devnull case 'P':
1062 a84cbb2a 2004-04-19 devnull n = ((i->spr&0x1f)<<5)|((i->spr>>5)&0x1f);
1063 a84cbb2a 2004-04-19 devnull for(s=0; sprname[s].name; s++)
1064 a84cbb2a 2004-04-19 devnull if(sprname[s].n == n)
1066 a84cbb2a 2004-04-19 devnull if(sprname[s].name) {
1067 a84cbb2a 2004-04-19 devnull if(s < 10)
1068 a84cbb2a 2004-04-19 devnull bprint(i, sprname[s].name);
1070 a84cbb2a 2004-04-19 devnull bprint(i, "SPR(%s)", sprname[s].name);
1072 a84cbb2a 2004-04-19 devnull bprint(i, "SPR(%d)", n);
1075 a84cbb2a 2004-04-19 devnull case 'n':
1076 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->nb==0? 32: i->nb); /* eg, pg 10-103 */
1079 a84cbb2a 2004-04-19 devnull case 'm':
1080 a84cbb2a 2004-04-19 devnull bprint(i, "%lx", i->crm);
1083 a84cbb2a 2004-04-19 devnull case 'M':
1084 a84cbb2a 2004-04-19 devnull bprint(i, "%lx", i->fm);
1087 a84cbb2a 2004-04-19 devnull case 'z':
1088 a84cbb2a 2004-04-19 devnull if(i->mb <= i->me)
1089 a84cbb2a 2004-04-19 devnull mask = ((ulong)~0L>>i->mb) & (~0L<<(31-i->me));
1091 a84cbb2a 2004-04-19 devnull mask = ~(((ulong)~0L>>(i->me+1)) & (~0L<<(31-(i->mb-1))));
1092 a84cbb2a 2004-04-19 devnull bprint(i, "%lux", mask);
1095 a84cbb2a 2004-04-19 devnull case 'k':
1096 a84cbb2a 2004-04-19 devnull bprint(i, "%d", i->sh);
1099 a84cbb2a 2004-04-19 devnull case 'K':
1100 a84cbb2a 2004-04-19 devnull bprint(i, "$%x", i->imm);
1103 a84cbb2a 2004-04-19 devnull case 'L':
1104 a84cbb2a 2004-04-19 devnull if(i->lk)
1105 a84cbb2a 2004-04-19 devnull bprint(i, "L");
1108 a84cbb2a 2004-04-19 devnull case 'j':
1109 a84cbb2a 2004-04-19 devnull if(i->aa)
1110 a84cbb2a 2004-04-19 devnull pglobal(i, i->li, 1, "(SB)");
1112 a84cbb2a 2004-04-19 devnull pglobal(i, i->addr+i->li, 1, "");
1115 a84cbb2a 2004-04-19 devnull case 'J':
1116 a84cbb2a 2004-04-19 devnull if(i->aa)
1117 a84cbb2a 2004-04-19 devnull pglobal(i, i->bd, 1, "(SB)");
1119 a84cbb2a 2004-04-19 devnull pglobal(i, i->addr+i->bd, 1, "");
1122 a84cbb2a 2004-04-19 devnull case '\0':
1123 a84cbb2a 2004-04-19 devnull bprint(i, "%%");
1124 a84cbb2a 2004-04-19 devnull return;
1126 a84cbb2a 2004-04-19 devnull default:
1127 a84cbb2a 2004-04-19 devnull bprint(i, "%%%c", *f);
1133 a84cbb2a 2004-04-19 devnull static int
1134 a84cbb2a 2004-04-19 devnull printins(Map *map, ulong pc, char *buf, int n)
1136 a84cbb2a 2004-04-19 devnull Instr i;
1137 a84cbb2a 2004-04-19 devnull Opcode *o;
1139 a84cbb2a 2004-04-19 devnull mymap = map;
1140 a84cbb2a 2004-04-19 devnull memset(&i, 0, sizeof(i));
1141 a84cbb2a 2004-04-19 devnull i.curr = buf;
1142 a84cbb2a 2004-04-19 devnull i.end = buf+n-1;
1143 a84cbb2a 2004-04-19 devnull if(mkinstr(pc, &i) < 0)
1144 a84cbb2a 2004-04-19 devnull return -1;
1145 a84cbb2a 2004-04-19 devnull for(o = opcodes; o->mnemonic != 0; o++)
1146 a84cbb2a 2004-04-19 devnull if(i.op == o->op && (i.xo & o->xomask) == o->xo) {
1147 a84cbb2a 2004-04-19 devnull if (o->f)
1148 a84cbb2a 2004-04-19 devnull (*o->f)(o, &i);
1150 a84cbb2a 2004-04-19 devnull format(o->mnemonic, &i, o->ken);
1151 a84cbb2a 2004-04-19 devnull return i.size*4;
1153 a84cbb2a 2004-04-19 devnull bprint(&i, "unknown %lux", i.w0);
1154 a84cbb2a 2004-04-19 devnull return i.size*4;
1157 a84cbb2a 2004-04-19 devnull static int
1158 443d6288 2012-02-19 rsc powerdas(Map *map, u64int pc, char modifier, char *buf, int n)
1160 a84cbb2a 2004-04-19 devnull USED(modifier);
1161 a84cbb2a 2004-04-19 devnull return printins(map, pc, buf, n);
1164 a84cbb2a 2004-04-19 devnull static int
1165 443d6288 2012-02-19 rsc powerhexinst(Map *map, u64int pc, char *buf, int n)
1167 a84cbb2a 2004-04-19 devnull Instr instr;
1169 a84cbb2a 2004-04-19 devnull mymap = map;
1170 a84cbb2a 2004-04-19 devnull memset(&instr, 0, sizeof(instr));
1171 a84cbb2a 2004-04-19 devnull instr.curr = buf;
1172 a84cbb2a 2004-04-19 devnull instr.end = buf+n-1;
1173 a84cbb2a 2004-04-19 devnull if (mkinstr(pc, &instr) < 0)
1174 a84cbb2a 2004-04-19 devnull return -1;
1175 a84cbb2a 2004-04-19 devnull if (instr.end-instr.curr > 8)
1176 a84cbb2a 2004-04-19 devnull instr.curr = _hexify(instr.curr, instr.w0, 7);
1177 a84cbb2a 2004-04-19 devnull if (instr.end-instr.curr > 9 && instr.size == 2) {
1178 a84cbb2a 2004-04-19 devnull *instr.curr++ = ' ';
1179 a84cbb2a 2004-04-19 devnull instr.curr = _hexify(instr.curr, instr.w1, 7);
1181 a84cbb2a 2004-04-19 devnull *instr.curr = 0;
1182 a84cbb2a 2004-04-19 devnull return instr.size*4;
1185 a84cbb2a 2004-04-19 devnull static int
1186 443d6288 2012-02-19 rsc powerinstlen(Map *map, u64int pc)
1188 a84cbb2a 2004-04-19 devnull Instr i;
1190 a84cbb2a 2004-04-19 devnull mymap = map;
1191 a84cbb2a 2004-04-19 devnull if (mkinstr(pc, &i) < 0)
1192 a84cbb2a 2004-04-19 devnull return -1;
1193 a84cbb2a 2004-04-19 devnull return i.size*4;
1196 a84cbb2a 2004-04-19 devnull static int
1197 443d6288 2012-02-19 rsc powerfoll(Map *map, Regs *regs, u64int pc, u64int *foll)
1199 a84cbb2a 2004-04-19 devnull char *reg;
1200 a84cbb2a 2004-04-19 devnull Instr i;
1202 a84cbb2a 2004-04-19 devnull mymap = map;
1203 a84cbb2a 2004-04-19 devnull if (mkinstr(pc, &i) < 0)
1204 a84cbb2a 2004-04-19 devnull return -1;
1205 a84cbb2a 2004-04-19 devnull foll[0] = pc+4;
1206 a84cbb2a 2004-04-19 devnull foll[1] = pc+4;
1207 a84cbb2a 2004-04-19 devnull switch(i.op) {
1208 a84cbb2a 2004-04-19 devnull default:
1209 a84cbb2a 2004-04-19 devnull return 1;
1211 a84cbb2a 2004-04-19 devnull case 18: /* branch */
1212 a84cbb2a 2004-04-19 devnull foll[0] = i.li;
1213 a84cbb2a 2004-04-19 devnull if(!i.aa)
1214 a84cbb2a 2004-04-19 devnull foll[0] += pc;
1217 a84cbb2a 2004-04-19 devnull case 16: /* conditional branch */
1218 a84cbb2a 2004-04-19 devnull foll[0] = i.bd;
1219 a84cbb2a 2004-04-19 devnull if(!i.aa)
1220 a84cbb2a 2004-04-19 devnull foll[0] += pc;
1223 a84cbb2a 2004-04-19 devnull case 19: /* conditional branch to register */
1224 a84cbb2a 2004-04-19 devnull if(i.xo == 528)
1225 a84cbb2a 2004-04-19 devnull reg = "CTR";
1226 a84cbb2a 2004-04-19 devnull else if(i.xo == 16)
1227 a84cbb2a 2004-04-19 devnull reg = "LR";
1229 a84cbb2a 2004-04-19 devnull return 1; /* not a branch */
1230 a84cbb2a 2004-04-19 devnull if(rget(regs, reg, &foll[0]) < 0)
1231 a84cbb2a 2004-04-19 devnull return -1;
1234 a84cbb2a 2004-04-19 devnull if(i.lk)
1235 a84cbb2a 2004-04-19 devnull return 2;
1236 a84cbb2a 2004-04-19 devnull return 1;
1239 a84cbb2a 2004-04-19 devnull #define REGOFF(x) (ulong) (&((struct Ureg *) 0)->x)
1241 a84cbb2a 2004-04-19 devnull #define SP REGOFF(r1)
1242 a84cbb2a 2004-04-19 devnull #define PC REGOFF(pc)
1243 a84cbb2a 2004-04-19 devnull #define R3 REGOFF(r3) /* return reg */
1244 a84cbb2a 2004-04-19 devnull #define LR REGOFF(lr)
1245 a84cbb2a 2004-04-19 devnull #define R31 REGOFF(r31)
1246 a84cbb2a 2004-04-19 devnull #define FP_REG(x) (R31+4+8*(x))
1248 a84cbb2a 2004-04-19 devnull #define REGSIZE sizeof(struct Ureg)
1249 fa325e9b 2020-01-10 cross #define FPREGSIZE (8*33)
1251 a84cbb2a 2004-04-19 devnull Regdesc powerreglist[] =
1253 a84cbb2a 2004-04-19 devnull {"CAUSE", REGOFF(cause), RINT|RRDONLY, 'X'},
1254 a84cbb2a 2004-04-19 devnull {"SRR1", REGOFF(srr1), RINT|RRDONLY, 'X'},
1255 a84cbb2a 2004-04-19 devnull {"PC", REGOFF(pc), RINT, 'X'},
1256 a84cbb2a 2004-04-19 devnull {"LR", REGOFF(lr), RINT, 'X'},
1257 a84cbb2a 2004-04-19 devnull {"CR", REGOFF(cr), RINT, 'X'},
1258 a84cbb2a 2004-04-19 devnull {"XER", REGOFF(xer), RINT, 'X'},
1259 a84cbb2a 2004-04-19 devnull {"CTR", REGOFF(ctr), RINT, 'X'},
1260 a84cbb2a 2004-04-19 devnull {"PC", PC, RINT, 'X'},
1261 a84cbb2a 2004-04-19 devnull {"SP", SP, RINT, 'X'},
1262 a84cbb2a 2004-04-19 devnull {"R0", REGOFF(r0), RINT, 'X'},
1263 a84cbb2a 2004-04-19 devnull /* R1 is SP */
1264 a84cbb2a 2004-04-19 devnull {"R2", REGOFF(r2), RINT, 'X'},
1265 a84cbb2a 2004-04-19 devnull {"R3", REGOFF(r3), RINT, 'X'},
1266 a84cbb2a 2004-04-19 devnull {"R4", REGOFF(r4), RINT, 'X'},
1267 a84cbb2a 2004-04-19 devnull {"R5", REGOFF(r5), RINT, 'X'},
1268 a84cbb2a 2004-04-19 devnull {"R6", REGOFF(r6), RINT, 'X'},
1269 a84cbb2a 2004-04-19 devnull {"R7", REGOFF(r7), RINT, 'X'},
1270 a84cbb2a 2004-04-19 devnull {"R8", REGOFF(r8), RINT, 'X'},
1271 a84cbb2a 2004-04-19 devnull {"R9", REGOFF(r9), RINT, 'X'},
1272 a84cbb2a 2004-04-19 devnull {"R10", REGOFF(r10), RINT, 'X'},
1273 a84cbb2a 2004-04-19 devnull {"R11", REGOFF(r11), RINT, 'X'},
1274 a84cbb2a 2004-04-19 devnull {"R12", REGOFF(r12), RINT, 'X'},
1275 a84cbb2a 2004-04-19 devnull {"R13", REGOFF(r13), RINT, 'X'},
1276 a84cbb2a 2004-04-19 devnull {"R14", REGOFF(r14), RINT, 'X'},
1277 a84cbb2a 2004-04-19 devnull {"R15", REGOFF(r15), RINT, 'X'},
1278 a84cbb2a 2004-04-19 devnull {"R16", REGOFF(r16), RINT, 'X'},
1279 a84cbb2a 2004-04-19 devnull {"R17", REGOFF(r17), RINT, 'X'},
1280 a84cbb2a 2004-04-19 devnull {"R18", REGOFF(r18), RINT, 'X'},
1281 a84cbb2a 2004-04-19 devnull {"R19", REGOFF(r19), RINT, 'X'},
1282 a84cbb2a 2004-04-19 devnull {"R20", REGOFF(r20), RINT, 'X'},
1283 a84cbb2a 2004-04-19 devnull {"R21", REGOFF(r21), RINT, 'X'},
1284 a84cbb2a 2004-04-19 devnull {"R22", REGOFF(r22), RINT, 'X'},
1285 a84cbb2a 2004-04-19 devnull {"R23", REGOFF(r23), RINT, 'X'},
1286 a84cbb2a 2004-04-19 devnull {"R24", REGOFF(r24), RINT, 'X'},
1287 a84cbb2a 2004-04-19 devnull {"R25", REGOFF(r25), RINT, 'X'},
1288 a84cbb2a 2004-04-19 devnull {"R26", REGOFF(r26), RINT, 'X'},
1289 a84cbb2a 2004-04-19 devnull {"R27", REGOFF(r27), RINT, 'X'},
1290 a84cbb2a 2004-04-19 devnull {"R28", REGOFF(r28), RINT, 'X'},
1291 a84cbb2a 2004-04-19 devnull {"R29", REGOFF(r29), RINT, 'X'},
1292 a84cbb2a 2004-04-19 devnull {"R30", REGOFF(r30), RINT, 'X'},
1293 a84cbb2a 2004-04-19 devnull {"R31", REGOFF(r31), RINT, 'X'},
1294 a84cbb2a 2004-04-19 devnull {"VRSAVE", REGOFF(vrsave), RINT, 'X'},
1295 a84cbb2a 2004-04-19 devnull {"F0", FP_REG(0), RFLT, 'F'},
1296 a84cbb2a 2004-04-19 devnull {"F1", FP_REG(1), RFLT, 'F'},
1297 a84cbb2a 2004-04-19 devnull {"F2", FP_REG(2), RFLT, 'F'},
1298 a84cbb2a 2004-04-19 devnull {"F3", FP_REG(3), RFLT, 'F'},
1299 a84cbb2a 2004-04-19 devnull {"F4", FP_REG(4), RFLT, 'F'},
1300 a84cbb2a 2004-04-19 devnull {"F5", FP_REG(5), RFLT, 'F'},
1301 a84cbb2a 2004-04-19 devnull {"F6", FP_REG(6), RFLT, 'F'},
1302 a84cbb2a 2004-04-19 devnull {"F7", FP_REG(7), RFLT, 'F'},
1303 a84cbb2a 2004-04-19 devnull {"F8", FP_REG(8), RFLT, 'F'},
1304 a84cbb2a 2004-04-19 devnull {"F9", FP_REG(9), RFLT, 'F'},
1305 a84cbb2a 2004-04-19 devnull {"F10", FP_REG(10), RFLT, 'F'},
1306 a84cbb2a 2004-04-19 devnull {"F11", FP_REG(11), RFLT, 'F'},
1307 a84cbb2a 2004-04-19 devnull {"F12", FP_REG(12), RFLT, 'F'},
1308 a84cbb2a 2004-04-19 devnull {"F13", FP_REG(13), RFLT, 'F'},
1309 a84cbb2a 2004-04-19 devnull {"F14", FP_REG(14), RFLT, 'F'},
1310 a84cbb2a 2004-04-19 devnull {"F15", FP_REG(15), RFLT, 'F'},
1311 a84cbb2a 2004-04-19 devnull {"F16", FP_REG(16), RFLT, 'F'},
1312 a84cbb2a 2004-04-19 devnull {"F17", FP_REG(17), RFLT, 'F'},
1313 a84cbb2a 2004-04-19 devnull {"F18", FP_REG(18), RFLT, 'F'},
1314 a84cbb2a 2004-04-19 devnull {"F19", FP_REG(19), RFLT, 'F'},
1315 a84cbb2a 2004-04-19 devnull {"F20", FP_REG(20), RFLT, 'F'},
1316 a84cbb2a 2004-04-19 devnull {"F21", FP_REG(21), RFLT, 'F'},
1317 a84cbb2a 2004-04-19 devnull {"F22", FP_REG(22), RFLT, 'F'},
1318 a84cbb2a 2004-04-19 devnull {"F23", FP_REG(23), RFLT, 'F'},
1319 a84cbb2a 2004-04-19 devnull {"F24", FP_REG(24), RFLT, 'F'},
1320 a84cbb2a 2004-04-19 devnull {"F25", FP_REG(25), RFLT, 'F'},
1321 a84cbb2a 2004-04-19 devnull {"F26", FP_REG(26), RFLT, 'F'},
1322 a84cbb2a 2004-04-19 devnull {"F27", FP_REG(27), RFLT, 'F'},
1323 a84cbb2a 2004-04-19 devnull {"F28", FP_REG(28), RFLT, 'F'},
1324 a84cbb2a 2004-04-19 devnull {"F29", FP_REG(29), RFLT, 'F'},
1325 a84cbb2a 2004-04-19 devnull {"F30", FP_REG(30), RFLT, 'F'},
1326 a84cbb2a 2004-04-19 devnull {"F31", FP_REG(31), RFLT, 'F'},
1327 a84cbb2a 2004-04-19 devnull {"FPSCR", FP_REG(32)+4, RFLT, 'X'},
1331 fa325e9b 2020-01-10 cross static char *powerwindregs[] =
1339 a84cbb2a 2004-04-19 devnull static int
1340 443d6288 2012-02-19 rsc powerunwind(Map *map, Regs *regs, u64int *next, Symbol *sym)
1343 a84cbb2a 2004-04-19 devnull * This is tremendously hard. The best we're going to
1344 a84cbb2a 2004-04-19 devnull * do without better debugger support is trace through
1345 a84cbb2a 2004-04-19 devnull * the stack frame links and pull the link registers out of 8(R1).
1346 a84cbb2a 2004-04-19 devnull * Anything more requires knowing which registers got saved,
1347 a84cbb2a 2004-04-19 devnull * and the compiler appears not to record that. Gdb appears
1348 a84cbb2a 2004-04-19 devnull * to disassemble the function prologues in order to figure
1349 a84cbb2a 2004-04-19 devnull * this out.
1351 cbeb0b26 2006-04-01 devnull /* evaluate lr */
1352 cbeb0b26 2006-04-01 devnull /* if in this function, no good - go to saved one. */
1353 cbeb0b26 2006-04-01 devnull /* set next[sp] to *cur[sp] */
1354 cbeb0b26 2006-04-01 devnull /* set next[pc] to lr */
1355 cbeb0b26 2006-04-01 devnull /* set next[lr] to lr */
1357 a84cbb2a 2004-04-19 devnull werrstr("powerunwind not implemented");
1358 a84cbb2a 2004-04-19 devnull return -1;
1361 a84cbb2a 2004-04-19 devnull /* the machine description */
1362 a84cbb2a 2004-04-19 devnull Mach machpower =
1364 a84cbb2a 2004-04-19 devnull "power",
1365 a84cbb2a 2004-04-19 devnull MPOWER, /* machine type */
1366 a84cbb2a 2004-04-19 devnull powerreglist, /* register set */
1367 a84cbb2a 2004-04-19 devnull REGSIZE, /* number of bytes in register set */
1368 a84cbb2a 2004-04-19 devnull FPREGSIZE, /* number of bytes in FP register set */
1369 a84cbb2a 2004-04-19 devnull "PC", /* name of PC */
1370 a84cbb2a 2004-04-19 devnull "SP", /* name of SP */
1371 a84cbb2a 2004-04-19 devnull 0, /* name of FP */
1372 a84cbb2a 2004-04-19 devnull "LR", /* name of link register */
1373 a84cbb2a 2004-04-19 devnull "setSB", /* static base register name */
1374 a84cbb2a 2004-04-19 devnull 0, /* value */
1375 a84cbb2a 2004-04-19 devnull 0x1000, /* page size */
1376 a84cbb2a 2004-04-19 devnull 0x80000000, /* kernel base */
1377 a84cbb2a 2004-04-19 devnull 0, /* kernel text mask */
1378 a84cbb2a 2004-04-19 devnull 4, /* quantization of pc */
1379 a84cbb2a 2004-04-19 devnull 4, /* szaddr */
1380 a84cbb2a 2004-04-19 devnull 4, /* szreg */
1381 a84cbb2a 2004-04-19 devnull 4, /* szfloat */
1382 a84cbb2a 2004-04-19 devnull 8, /* szdouble */
1384 a84cbb2a 2004-04-19 devnull powerwindregs, /* locations unwound in stack trace */
1387 a84cbb2a 2004-04-19 devnull {0x02, 0x8F, 0xFF, 0xFF}, /* break point */ /* BUG */
1390 a84cbb2a 2004-04-19 devnull powerfoll, /* following addresses */
1391 a84cbb2a 2004-04-19 devnull powerexcep, /* print exception */
1392 a84cbb2a 2004-04-19 devnull powerunwind, /* stack unwind */
1394 a84cbb2a 2004-04-19 devnull beswap2, /* convert short to local byte order */
1395 a84cbb2a 2004-04-19 devnull beswap4, /* convert long to local byte order */
1396 a84cbb2a 2004-04-19 devnull beswap8, /* convert vlong to local byte order */
1397 a84cbb2a 2004-04-19 devnull beieeeftoa32, /* single precision float pointer */
1398 a84cbb2a 2004-04-19 devnull beieeeftoa64, /* double precision float pointer */
1399 a84cbb2a 2004-04-19 devnull beieeeftoa80, /* long double precision floating point */
1401 a84cbb2a 2004-04-19 devnull powerdas, /* dissembler */
1402 a84cbb2a 2004-04-19 devnull powerdas, /* plan9-format disassembler */
1403 a84cbb2a 2004-04-19 devnull 0, /* commercial disassembler */
1404 a84cbb2a 2004-04-19 devnull powerhexinst, /* print instruction */
1405 a84cbb2a 2004-04-19 devnull powerinstlen, /* instruction size calculation */
