1 cfa37a7b 2004-04-10 devnull .TH GETFCR 3
3 cfa37a7b 2004-04-10 devnull getfcr, setfcr, getfsr, setfsr \- control floating point
4 cfa37a7b 2004-04-10 devnull .SH SYNOPSIS
5 cfa37a7b 2004-04-10 devnull .B #include <u.h>
7 cfa37a7b 2004-04-10 devnull .B #include <libc.h>
10 cfa37a7b 2004-04-10 devnull ulong getfcr(void)
13 cfa37a7b 2004-04-10 devnull void setfcr(ulong fcr)
16 cfa37a7b 2004-04-10 devnull ulong getfsr(void)
19 cfa37a7b 2004-04-10 devnull void setfsr(ulong fsr)
20 cfa37a7b 2004-04-10 devnull .SH DESCRIPTION
21 cfa37a7b 2004-04-10 devnull These routines provide a fairly portable interface to control the
22 cfa37a7b 2004-04-10 devnull rounding and exception characteristics of IEEE 754 floating point units.
23 cfa37a7b 2004-04-10 devnull In effect, they define a pair of pseudo-registers, the floating
24 cfa37a7b 2004-04-10 devnull point control register,
25 cfa37a7b 2004-04-10 devnull .BR fcr ,
26 cfa37a7b 2004-04-10 devnull which affects rounding, precision, and exceptions, and the
27 cfa37a7b 2004-04-10 devnull floating point status register,
28 cfa37a7b 2004-04-10 devnull .BR fsr ,
29 cfa37a7b 2004-04-10 devnull which holds the accrued exception bits.
30 cfa37a7b 2004-04-10 devnull Each register has a
32 cfa37a7b 2004-04-10 devnull routine to retrieve its value, a
34 cfa37a7b 2004-04-10 devnull routine to modify it,
35 cfa37a7b 2004-04-10 devnull and macros that identify its contents.
39 cfa37a7b 2004-04-10 devnull contains bits that, when set, halt execution upon exceptions:
40 cfa37a7b 2004-04-10 devnull .B FPINEX
41 cfa37a7b 2004-04-10 devnull (enable inexact exceptions),
42 cfa37a7b 2004-04-10 devnull .B FPOVFL
43 cfa37a7b 2004-04-10 devnull (enable overflow exceptions),
44 cfa37a7b 2004-04-10 devnull .B FPUNFL
45 cfa37a7b 2004-04-10 devnull (enable underflow exceptions),
46 cfa37a7b 2004-04-10 devnull .B FPZDIV
47 cfa37a7b 2004-04-10 devnull (enable zero divide exceptions), and
48 cfa37a7b 2004-04-10 devnull .B FPINVAL
49 cfa37a7b 2004-04-10 devnull (enable invalid operation exceptions).
50 cfa37a7b 2004-04-10 devnull Rounding is controlled by installing in
51 cfa37a7b 2004-04-10 devnull .BR fcr ,
52 cfa37a7b 2004-04-10 devnull under mask
53 cfa37a7b 2004-04-10 devnull .BR FPRMASK ,
54 cfa37a7b 2004-04-10 devnull one of the values
56 cfa37a7b 2004-04-10 devnull (round to nearest),
58 cfa37a7b 2004-04-10 devnull (round towards zero),
59 cfa37a7b 2004-04-10 devnull .B FPRPINF
60 cfa37a7b 2004-04-10 devnull (round towards positive infinity), and
61 cfa37a7b 2004-04-10 devnull .B FPRNINF
62 cfa37a7b 2004-04-10 devnull (round towards negative infinity).
63 cfa37a7b 2004-04-10 devnull Precision is controlled by installing in
64 cfa37a7b 2004-04-10 devnull .BR fcr ,
65 cfa37a7b 2004-04-10 devnull under mask
66 cfa37a7b 2004-04-10 devnull .BR FPPMASK ,
67 cfa37a7b 2004-04-10 devnull one of the values
68 cfa37a7b 2004-04-10 devnull .B FPPEXT
69 cfa37a7b 2004-04-10 devnull (extended precision),
70 cfa37a7b 2004-04-10 devnull .B FPPSGL
71 cfa37a7b 2004-04-10 devnull (single precision), and
72 cfa37a7b 2004-04-10 devnull .B FPPDBL
73 cfa37a7b 2004-04-10 devnull (double precision).
77 cfa37a7b 2004-04-10 devnull holds the accrued exception bits
78 cfa37a7b 2004-04-10 devnull .BR FPAINEX ,
79 cfa37a7b 2004-04-10 devnull .BR FPAOVFL ,
80 cfa37a7b 2004-04-10 devnull .BR FPAUNFL ,
81 cfa37a7b 2004-04-10 devnull .BR FPAZDIV ,
83 cfa37a7b 2004-04-10 devnull .BR FPAINVAL ,
84 cfa37a7b 2004-04-10 devnull corresponding to the
86 cfa37a7b 2004-04-10 devnull bits without the
88 cfa37a7b 2004-04-10 devnull in the name.
90 cfa37a7b 2004-04-10 devnull Not all machines support all modes. If the corresponding mask
91 cfa37a7b 2004-04-10 devnull is zero, the machine does not support the rounding or precision modes.
92 cfa37a7b 2004-04-10 devnull On some machines it is not possible to clear selective accrued
93 cfa37a7b 2004-04-10 devnull exception bits; a
94 cfa37a7b 2004-04-10 devnull .I setfsr
95 cfa37a7b 2004-04-10 devnull clears them all.
96 cfa37a7b 2004-04-10 devnull The exception bits defined here work on all architectures.
97 cfa37a7b 2004-04-10 devnull By default, the initial state is equivalent to
100 cfa37a7b 2004-04-10 devnull setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
103 cfa37a7b 2004-04-10 devnull The default state of the floating point unit is fixed for a given
104 cfa37a7b 2004-04-10 devnull architecture but is undefined across Plan 9: the default is
105 cfa37a7b 2004-04-10 devnull to provide what the hardware does most efficiently.
106 cfa37a7b 2004-04-10 devnull Use these routines
107 cfa37a7b 2004-04-10 devnull if you need guaranteed behavior.
108 cfa37a7b 2004-04-10 devnull Also, gradual underflow is not available on some machines.
109 cfa37a7b 2004-04-10 devnull .SH EXAMPLE
110 cfa37a7b 2004-04-10 devnull To enable overflow traps and make sure registers are rounded
111 cfa37a7b 2004-04-10 devnull to double precision (for example on the MC68020, where the
112 cfa37a7b 2004-04-10 devnull internal registers are 80 bits long):
116 cfa37a7b 2004-04-10 devnull ulong fcr;
117 cfa37a7b 2004-04-10 devnull fcr = getfcr();
118 cfa37a7b 2004-04-10 devnull fcr |= FPOVFL;
119 cfa37a7b 2004-04-10 devnull fcr &= ~FPPMASK;
120 cfa37a7b 2004-04-10 devnull fcr |= FPPDBL;
121 cfa37a7b 2004-04-10 devnull setfcr(fcr);
124 cfa37a7b 2004-04-10 devnull .SH SOURCE
125 b5fdffee 2004-04-19 devnull .B /usr/local/plan9/src/libc/$objtype/getfcr.s
