1 ac0e2db6 2004-04-21 devnull /*
 2 ac0e2db6 2004-04-21 devnull  *	mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
 3 ac0e2db6 2004-04-21 devnull  *
 4 ac0e2db6 2004-04-21 devnull  *	p -= b*m
 5 ac0e2db6 2004-04-21 devnull  *
 6 ac0e2db6 2004-04-21 devnull  *	each step look like:
 7 ac0e2db6 2004-04-21 devnull  *		hi,lo = m*b[i]
 8 ac0e2db6 2004-04-21 devnull  *		lo += oldhi + carry
 9 ac0e2db6 2004-04-21 devnull  *		hi += carry
10 ac0e2db6 2004-04-21 devnull  *		p[i] += lo
11 ac0e2db6 2004-04-21 devnull  *		oldhi = hi
12 ac0e2db6 2004-04-21 devnull  *
13 ac0e2db6 2004-04-21 devnull  *	the registers are:
14 ac0e2db6 2004-04-21 devnull  *		hi = DX		- constrained by hardware
15 ac0e2db6 2004-04-21 devnull  *		lo = AX		- constrained by hardware
16 ac0e2db6 2004-04-21 devnull  *		b = SI		- can't be BP
17 ac0e2db6 2004-04-21 devnull  *		p = DI		- can't be BP
18 ac0e2db6 2004-04-21 devnull  *		i = BP
19 ac0e2db6 2004-04-21 devnull  *		n = CX		- constrained by LOOP instr
20 ac0e2db6 2004-04-21 devnull  *		m = BX
21 ac0e2db6 2004-04-21 devnull  *		oldhi = EX
22 ac0e2db6 2004-04-21 devnull  *		
23 ac0e2db6 2004-04-21 devnull  */
24 ac0e2db6 2004-04-21 devnull .text
25 ac0e2db6 2004-04-21 devnull 
26 ac0e2db6 2004-04-21 devnull .p2align 2,0x90
27 ac0e2db6 2004-04-21 devnull .globl mpvecdigmulsub
28 ac0e2db6 2004-04-21 devnull mpvecdigmulsub:
29 ac0e2db6 2004-04-21 devnull 	/* Prelude */
30 bdc14ad4 2006-03-22 devnull 	pushl %ebp		/* save on stack */
31 bdc14ad4 2006-03-22 devnull 	pushl %ebx
32 bdc14ad4 2006-03-22 devnull 	pushl %esi
33 bdc14ad4 2006-03-22 devnull 	pushl %edi
34 ac0e2db6 2004-04-21 devnull 
35 bdc14ad4 2006-03-22 devnull 	leal 20(%esp), %ebp		/* %ebp = FP for now */
36 bdc14ad4 2006-03-22 devnull 	movl	0(%ebp), %esi		/* b */
37 bdc14ad4 2006-03-22 devnull 	movl	4(%ebp), %ecx		/* n */
38 bdc14ad4 2006-03-22 devnull 	movl	8(%ebp), %ebx		/* m */
39 bdc14ad4 2006-03-22 devnull 	movl	12(%ebp), %edi		/* p */
40 ac0e2db6 2004-04-21 devnull 	xorl	%ebp, %ebp
41 bdc14ad4 2006-03-22 devnull 	pushl %ebp
42 ac0e2db6 2004-04-21 devnull _mulsubloop:
43 ac0e2db6 2004-04-21 devnull 	movl	(%esi, %ebp, 4),%eax	/* lo = b[i] */
44 ac0e2db6 2004-04-21 devnull 	mull	%ebx			/* hi, lo = b[i] * m */
45 bdc14ad4 2006-03-22 devnull 	addl	0(%esp), %eax		/* lo += oldhi */
46 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry1
47 ac0e2db6 2004-04-21 devnull 	incl	%edx			/* hi += carry */
48 ac0e2db6 2004-04-21 devnull _mulsubnocarry1:
49 ac0e2db6 2004-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
50 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry2
51 ac0e2db6 2004-04-21 devnull 	incl	%edx			/* hi += carry */
52 ac0e2db6 2004-04-21 devnull _mulsubnocarry2:
53 bdc14ad4 2006-03-22 devnull 	movl	%edx, 0(%esp)
54 ac0e2db6 2004-04-21 devnull 	incl	%ebp
55 ac0e2db6 2004-04-21 devnull 	loop	_mulsubloop
56 bdc14ad4 2006-03-22 devnull 	popl %eax
57 ac0e2db6 2004-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
58 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry3
59 ac0e2db6 2004-04-21 devnull 	movl	$-1, %eax
60 ac0e2db6 2004-04-21 devnull 	jmp done
61 ac0e2db6 2004-04-21 devnull _mulsubnocarry3:
62 ac0e2db6 2004-04-21 devnull 	movl	$1, %eax
63 ac0e2db6 2004-04-21 devnull done:
64 ac0e2db6 2004-04-21 devnull 	/* Postlude */
65 bdc14ad4 2006-03-22 devnull 	popl %edi
66 bdc14ad4 2006-03-22 devnull 	popl %esi
67 bdc14ad4 2006-03-22 devnull 	popl %ebx
68 bdc14ad4 2006-03-22 devnull 	popl %ebp
69 ac0e2db6 2004-04-21 devnull 	ret
70 bdc14ad4 2006-03-22 devnull