Blob


1 // ARM7500 support
3 defn acidinit() // Called after all the init modules are loaded
4 {
5 bplist = {};
6 bpfmt = 'b';
8 srcpath = {
9 "./",
10 "/sys/src/libc/port/",
11 "/sys/src/libc/9sys/",
12 "/sys/src/libc/arm/"
13 };
15 srcfiles = {}; // list of loaded files
16 srctext = {}; // the text of the files
17 }
19 defn linkreg(addr)
20 {
21 return 0;
22 }
24 defn stk() // trace
25 {
26 _stk(*PC, *SP, 0, 0);
27 }
29 defn lstk() // trace with locals
30 {
31 _stk(*PC, *SP, 0, 1);
32 }
34 defn gpr() // print general purpose registers
35 {
36 print("R0\t", *R0, " R1\t", *R1, " R2\t", *R2, "\n");
37 print("R3\t", *R3, " R4\t", *R4, " R5\t", *R5, "\n");
38 print("R6\t", *R6, " R7\t", *R7, " R8\t", *R8, "\n");
39 print("R9\t", *R9, " R10\t", *R10, " R11\t", *R11, "\n");
40 print("R12\t", *R12, " R13\t", *R13, " R14\t", *R14, "\n");
41 print("R15\t", *R15, "\n");
42 }
44 defn regs() // print all registers
45 {
46 gpr();
47 }
49 defn pstop(pid)
50 {
51 return 0;
52 }
54 aggr Ureg
55 {
56 'U' 0 r0;
57 'U' 4 r1;
58 'U' 8 r2;
59 'U' 12 r3;
60 'U' 16 r4;
61 'U' 20 r5;
62 'U' 24 r6;
63 'U' 28 r7;
64 'U' 32 r8;
65 'U' 36 r9;
66 'U' 40 r10;
67 'U' 44 r11;
68 'U' 48 r12;
69 'U' 52 r13;
70 'U' 56 r14;
71 'U' 60 type;
72 'U' 64 psr;
73 'U' 68 pc;
74 };
76 defn
77 Ureg(addr) {
78 complex Ureg addr;
79 print(" r0 ", addr.r0, "\n");
80 print(" r1 ", addr.r1, "\n");
81 print(" r2 ", addr.r2, "\n");
82 print(" r3 ", addr.r3, "\n");
83 print(" r4 ", addr.r4, "\n");
84 print(" r5 ", addr.r5, "\n");
85 print(" r6 ", addr.r6, "\n");
86 print(" r7 ", addr.r7, "\n");
87 print(" r8 ", addr.r8, "\n");
88 print(" r9 ", addr.r9, "\n");
89 print(" r10 ", addr.r10, "\n");
90 print(" r11 ", addr.r11, "\n");
91 print(" r12 ", addr.r12, "\n");
92 print(" r13 ", addr.r13, "\n");
93 print(" r14 ", addr.r14, "\n");
94 print(" type ", addr.type, "\n");
95 print(" psr ", addr.psr, "\n");
96 print(" pc ", addr.pc, "\n");
97 };
99 defn acornmap()
101 map({"text", _startup, end, 0x20});
104 print(acidfile);