1 af0dea45 2011-05-17 rsc #
 2 af0dea45 2011-05-17 rsc #	mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
 3 af0dea45 2011-05-17 rsc #
 4 af0dea45 2011-05-17 rsc #	p -= b*m
 5 af0dea45 2011-05-17 rsc #
 6 af0dea45 2011-05-17 rsc #	each step look like:
 7 af0dea45 2011-05-17 rsc #		hi,lo = m*b[i]
 8 af0dea45 2011-05-17 rsc #		lo += oldhi + carry
 9 af0dea45 2011-05-17 rsc #		hi += carry
10 af0dea45 2011-05-17 rsc #		p[i] += lo
11 af0dea45 2011-05-17 rsc #		oldhi = hi
12 af0dea45 2011-05-17 rsc #
13 af0dea45 2011-05-17 rsc #	the registers are:
14 af0dea45 2011-05-17 rsc #		hi = DX		- constrained by hardware
15 af0dea45 2011-05-17 rsc #		lo = AX		- constrained by hardware
16 af0dea45 2011-05-17 rsc #		b = SI		- can't be BP
17 af0dea45 2011-05-17 rsc #		p = DI		- can't be BP
18 af0dea45 2011-05-17 rsc #		i = BP
19 af0dea45 2011-05-17 rsc #		n = CX		- constrained by LOOP instr
20 af0dea45 2011-05-17 rsc #		m = BX
21 af0dea45 2011-05-17 rsc #		oldhi = EX
22 af0dea45 2011-05-17 rsc #		
23 af0dea45 2011-05-17 rsc  
24 ac0e2db6 2004-04-21 devnull .text
25 ac0e2db6 2004-04-21 devnull 
26 ac0e2db6 2004-04-21 devnull .p2align 2,0x90
27 ac0e2db6 2004-04-21 devnull .globl mpvecdigmulsub
28 ac0e2db6 2004-04-21 devnull mpvecdigmulsub:
29 af0dea45 2011-05-17 rsc 	# Prelude 
30 af0dea45 2011-05-17 rsc 	pushl %ebp		# save on stack 
31 bdc14ad4 2006-03-22 devnull 	pushl %ebx
32 bdc14ad4 2006-03-22 devnull 	pushl %esi
33 bdc14ad4 2006-03-22 devnull 	pushl %edi
34 ac0e2db6 2004-04-21 devnull 
35 af0dea45 2011-05-17 rsc 	leal 20(%esp), %ebp		# %ebp = FP for now 
36 af0dea45 2011-05-17 rsc 	movl	0(%ebp), %esi		# b 
37 af0dea45 2011-05-17 rsc 	movl	4(%ebp), %ecx		# n 
38 af0dea45 2011-05-17 rsc 	movl	8(%ebp), %ebx		# m 
39 af0dea45 2011-05-17 rsc 	movl	12(%ebp), %edi		# p 
40 ac0e2db6 2004-04-21 devnull 	xorl	%ebp, %ebp
41 bdc14ad4 2006-03-22 devnull 	pushl %ebp
42 ac0e2db6 2004-04-21 devnull _mulsubloop:
43 af0dea45 2011-05-17 rsc 	movl	(%esi, %ebp, 4),%eax	# lo = b[i] 
44 af0dea45 2011-05-17 rsc 	mull	%ebx			# hi, lo = b[i] * m 
45 af0dea45 2011-05-17 rsc 	addl	0(%esp), %eax		# lo += oldhi 
46 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry1
47 af0dea45 2011-05-17 rsc 	incl	%edx			# hi += carry 
48 ac0e2db6 2004-04-21 devnull _mulsubnocarry1:
49 ac0e2db6 2004-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
50 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry2
51 af0dea45 2011-05-17 rsc 	incl	%edx			# hi += carry 
52 ac0e2db6 2004-04-21 devnull _mulsubnocarry2:
53 bdc14ad4 2006-03-22 devnull 	movl	%edx, 0(%esp)
54 ac0e2db6 2004-04-21 devnull 	incl	%ebp
55 ac0e2db6 2004-04-21 devnull 	loop	_mulsubloop
56 bdc14ad4 2006-03-22 devnull 	popl %eax
57 ac0e2db6 2004-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
58 ac0e2db6 2004-04-21 devnull 	jae	_mulsubnocarry3
59 ac0e2db6 2004-04-21 devnull 	movl	$-1, %eax
60 ac0e2db6 2004-04-21 devnull 	jmp done
61 ac0e2db6 2004-04-21 devnull _mulsubnocarry3:
62 ac0e2db6 2004-04-21 devnull 	movl	$1, %eax
63 ac0e2db6 2004-04-21 devnull done:
64 af0dea45 2011-05-17 rsc 	# Postlude 
65 bdc14ad4 2006-03-22 devnull 	popl %edi
66 bdc14ad4 2006-03-22 devnull 	popl %esi
67 bdc14ad4 2006-03-22 devnull 	popl %ebx
68 bdc14ad4 2006-03-22 devnull 	popl %ebp
69 ac0e2db6 2004-04-21 devnull 	ret
70 bdc14ad4 2006-03-22 devnull