1 af0dea45 2011-05-17 rsc #
 2 af0dea45 2011-05-17 rsc #	mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p)
 3 af0dea45 2011-05-17 rsc #
 4 af0dea45 2011-05-17 rsc #	p += b*m
 5 af0dea45 2011-05-17 rsc #
 6 af0dea45 2011-05-17 rsc #	each step look like:
 7 af0dea45 2011-05-17 rsc #		hi,lo = m*b[i]
 8 af0dea45 2011-05-17 rsc #		lo += oldhi + carry
 9 af0dea45 2011-05-17 rsc #		hi += carry
10 af0dea45 2011-05-17 rsc #		p[i] += lo
11 af0dea45 2011-05-17 rsc #		oldhi = hi
12 af0dea45 2011-05-17 rsc #
13 af0dea45 2011-05-17 rsc #	the registers are:
14 af0dea45 2011-05-17 rsc #		hi = DX		- constrained by hardware
15 af0dea45 2011-05-17 rsc #		lo = AX		- constrained by hardware
16 af0dea45 2011-05-17 rsc #		b+n = SI	- can't be BP
17 af0dea45 2011-05-17 rsc #		p+n = DI	- can't be BP
18 af0dea45 2011-05-17 rsc #		i-n = BP
19 af0dea45 2011-05-17 rsc #		m = BX
20 af0dea45 2011-05-17 rsc #		oldhi = CX
21 af0dea45 2011-05-17 rsc #		
22 af0dea45 2011-05-17 rsc  
23 ac0e2db6 2004-04-21 devnull .text
24 ac0e2db6 2004-04-21 devnull 
25 ac0e2db6 2004-04-21 devnull .p2align 2,0x90
26 ac0e2db6 2004-04-21 devnull .globl mpvecdigmuladd
27 ac0e2db6 2004-04-21 devnull mpvecdigmuladd:
28 af0dea45 2011-05-17 rsc 	# Prelude 
29 af0dea45 2011-05-17 rsc 	pushl %ebp		# save on stack 
30 39ce0d58 2006-03-22 devnull 	pushl %ebx
31 39ce0d58 2006-03-22 devnull 	pushl %esi
32 39ce0d58 2006-03-22 devnull 	pushl %edi
33 ac0e2db6 2004-04-21 devnull 
34 af0dea45 2011-05-17 rsc 	leal 20(%esp), %ebp		# %ebp = FP for now 
35 af0dea45 2011-05-17 rsc 	movl	0(%ebp), %esi		# b 
36 af0dea45 2011-05-17 rsc 	movl	4(%ebp), %ecx		# n 
37 af0dea45 2011-05-17 rsc 	movl	8(%ebp), %ebx		# m 
38 af0dea45 2011-05-17 rsc 	movl	12(%ebp), %edi		# p 
39 ac0e2db6 2004-04-21 devnull 	movl	%ecx, %ebp
40 af0dea45 2011-05-17 rsc 	negl	%ebp			# BP = -n 
41 ac0e2db6 2004-04-21 devnull 	shll	$2, %ecx
42 af0dea45 2011-05-17 rsc 	addl	%ecx, %esi		# SI = b + n 
43 af0dea45 2011-05-17 rsc 	addl	%ecx, %edi		# DI = p + n 
44 ac0e2db6 2004-04-21 devnull 	xorl	%ecx, %ecx
45 ac0e2db6 2004-04-21 devnull _muladdloop:
46 af0dea45 2011-05-17 rsc 	movl	(%esi, %ebp, 4), %eax	# lo = b[i] 
47 af0dea45 2011-05-17 rsc 	mull	%ebx			# hi, lo = b[i] * m 
48 af0dea45 2011-05-17 rsc 	addl	%ecx,%eax		# lo += oldhi 
49 ac0e2db6 2004-04-21 devnull 	jae	_muladdnocarry1
50 af0dea45 2011-05-17 rsc 	incl	%edx			# hi += carry 
51 ac0e2db6 2004-04-21 devnull _muladdnocarry1:
52 af0dea45 2011-05-17 rsc 	addl	%eax, (%edi, %ebp, 4)	# p[i] += lo 
53 ac0e2db6 2004-04-21 devnull 	jae	_muladdnocarry2
54 af0dea45 2011-05-17 rsc 	incl	%edx			# hi += carry 
55 ac0e2db6 2004-04-21 devnull _muladdnocarry2:
56 af0dea45 2011-05-17 rsc 	movl	%edx, %ecx		# oldhi = hi 
57 af0dea45 2011-05-17 rsc 	incl	%ebp			# i++ 
58 ac0e2db6 2004-04-21 devnull 	jnz	_muladdloop
59 ac0e2db6 2004-04-21 devnull 	xorl	%eax, %eax
60 af0dea45 2011-05-17 rsc 	addl	%ecx, (%edi, %ebp, 4)	# p[n] + oldhi 
61 af0dea45 2011-05-17 rsc 	adcl	%eax, %eax		# return carry out of p[n] 
62 ac0e2db6 2004-04-21 devnull 
63 af0dea45 2011-05-17 rsc 	# Postlude 
64 39ce0d58 2006-03-22 devnull 	popl %edi
65 39ce0d58 2006-03-22 devnull 	popl %esi
66 39ce0d58 2006-03-22 devnull 	popl %ebx
67 39ce0d58 2006-03-22 devnull 	popl %ebp
68 ac0e2db6 2004-04-21 devnull 	ret
69 39ce0d58 2006-03-22 devnull