1 4e3a81b9 2006-04-21 devnull /*
 2 4e3a81b9 2006-04-21 devnull  *	mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
 3 4e3a81b9 2006-04-21 devnull  *
 4 4e3a81b9 2006-04-21 devnull  *	p -= b*m
 5 4e3a81b9 2006-04-21 devnull  *
 6 4e3a81b9 2006-04-21 devnull  *	each step look like:
 7 4e3a81b9 2006-04-21 devnull  *		hi,lo = m*b[i]
 8 4e3a81b9 2006-04-21 devnull  *		lo += oldhi + carry
 9 4e3a81b9 2006-04-21 devnull  *		hi += carry
10 4e3a81b9 2006-04-21 devnull  *		p[i] += lo
11 4e3a81b9 2006-04-21 devnull  *		oldhi = hi
12 4e3a81b9 2006-04-21 devnull  *
13 4e3a81b9 2006-04-21 devnull  *	the registers are:
14 4e3a81b9 2006-04-21 devnull  *		hi = DX		- constrained by hardware
15 4e3a81b9 2006-04-21 devnull  *		lo = AX		- constrained by hardware
16 4e3a81b9 2006-04-21 devnull  *		b = SI		- can't be BP
17 4e3a81b9 2006-04-21 devnull  *		p = DI		- can't be BP
18 4e3a81b9 2006-04-21 devnull  *		i = BP
19 4e3a81b9 2006-04-21 devnull  *		n = CX		- constrained by LOOP instr
20 4e3a81b9 2006-04-21 devnull  *		m = BX
21 4e3a81b9 2006-04-21 devnull  *		oldhi = EX
22 4e3a81b9 2006-04-21 devnull  *		
23 4e3a81b9 2006-04-21 devnull  */
24 4e3a81b9 2006-04-21 devnull .text
25 4e3a81b9 2006-04-21 devnull 
26 4e3a81b9 2006-04-21 devnull .globl _mpvecdigmulsub
27 4e3a81b9 2006-04-21 devnull _mpvecdigmulsub:
28 4e3a81b9 2006-04-21 devnull 	/* Prelude */
29 4e3a81b9 2006-04-21 devnull 	pushl %ebp		/* save on stack */
30 4e3a81b9 2006-04-21 devnull 	pushl %ebx
31 4e3a81b9 2006-04-21 devnull 	pushl %esi
32 4e3a81b9 2006-04-21 devnull 	pushl %edi
33 4e3a81b9 2006-04-21 devnull 
34 4e3a81b9 2006-04-21 devnull 	leal 20(%esp), %ebp		/* %ebp = FP for now */
35 4e3a81b9 2006-04-21 devnull 	movl	0(%ebp), %esi		/* b */
36 4e3a81b9 2006-04-21 devnull 	movl	4(%ebp), %ecx		/* n */
37 4e3a81b9 2006-04-21 devnull 	movl	8(%ebp), %ebx		/* m */
38 4e3a81b9 2006-04-21 devnull 	movl	12(%ebp), %edi		/* p */
39 4e3a81b9 2006-04-21 devnull 	xorl	%ebp, %ebp
40 4e3a81b9 2006-04-21 devnull 	pushl %ebp
41 88cf5927 2007-11-05 rsc 1:
42 4e3a81b9 2006-04-21 devnull 	movl	(%esi, %ebp, 4),%eax	/* lo = b[i] */
43 4e3a81b9 2006-04-21 devnull 	mull	%ebx			/* hi, lo = b[i] * m */
44 4e3a81b9 2006-04-21 devnull 	addl	0(%esp), %eax		/* lo += oldhi */
45 88cf5927 2007-11-05 rsc 	jae	2f
46 4e3a81b9 2006-04-21 devnull 	incl	%edx			/* hi += carry */
47 88cf5927 2007-11-05 rsc 2:
48 4e3a81b9 2006-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
49 88cf5927 2007-11-05 rsc 	jae	3f
50 4e3a81b9 2006-04-21 devnull 	incl	%edx			/* hi += carry */
51 88cf5927 2007-11-05 rsc 3:
52 4e3a81b9 2006-04-21 devnull 	movl	%edx, 0(%esp)
53 4e3a81b9 2006-04-21 devnull 	incl	%ebp
54 88cf5927 2007-11-05 rsc 	loop	1b
55 4e3a81b9 2006-04-21 devnull 	popl %eax
56 4e3a81b9 2006-04-21 devnull 	subl	%eax, (%edi, %ebp, 4)
57 88cf5927 2007-11-05 rsc 	jae	4f
58 4e3a81b9 2006-04-21 devnull 	movl	$-1, %eax
59 88cf5927 2007-11-05 rsc 	jmp 5f
60 88cf5927 2007-11-05 rsc 4:
61 4e3a81b9 2006-04-21 devnull 	movl	$1, %eax
62 88cf5927 2007-11-05 rsc 5:
63 4e3a81b9 2006-04-21 devnull 	/* Postlude */
64 4e3a81b9 2006-04-21 devnull 	popl %edi
65 4e3a81b9 2006-04-21 devnull 	popl %esi
66 4e3a81b9 2006-04-21 devnull 	popl %ebx
67 4e3a81b9 2006-04-21 devnull 	popl %ebp
68 4e3a81b9 2006-04-21 devnull 	ret
69 4e3a81b9 2006-04-21 devnull